IDT77V126L200TFI8 IDT, Integrated Device Technology Inc, IDT77V126L200TFI8 Datasheet - Page 4

• Manufacturer Part Number: IDT77V126L200TFI8
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT77V126L200TFI8

• Number Of Channels: 1
• Type Of Atm Phy Interface: UTOPIA
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Pin Count: 64
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Signal Descriptions
RXD+, RXD-
TXD+, TXD-
AD[7:0]
ALE
CS
RD
WR
RXCLAV
RXCLK
RXDATA[7:0] 24, 25, 26,
RXEN
RXPARITY
RXSOC
TXCLAV
TXCLK
TXDATA[7:0]
TXEN
TXPARITY
TXSOC
Signal Name Pin Number
Signal Name Pin Number
Signal Name Pin Number
IDT77V126L200
58, 57
62, 61
48, 47, 46,
45, 43, 42,
41, 40
39
38
37
36
20
18
27, 29, 30,
31, 32
19
23
21
16
17
11, 10, 9, 8,
7, 6, 5, 4
13
12
14
In
Out
In/
Out
In
In
In
In
Out
In
Out
In
Out
Out
Out
In
In
In
In
In
I/O
I/O
I/O
Positive and negative receive differential input pair.
Utopia Receive Start of Cell. Asserted coincident with the first word of data for each cell on RXDATA.
Utopia Transmit Start of Cell. Asserted coincident with the first word of data for each cell on TXDATA.
Signal Description
Positive and negative transmit differential output pair.
Signal Description
Utility bus address/data bus. The address input is sampled on the falling edge of ALE. Data is output on this bus when a read
is performed. Input data is sampled at the completion of a write operation.
Utility bus address latch enable. Asynchronous input. An address on the AD bus is sampled on the falling edge of ALE. ALE
must be low when the AD bus is being used for data.
Utility bus asynchronous chip select. CS must be asserted to read or write an internal register. It may remain asserted at all
times if desired.
Utility bus read enable. Active low asynchronous input. After latching an address, a read is performed by deasserting WR
and asserting RD and CS.
Utility bus write enable. Active low asynchronous input. After latching an address, a write is performed by deasserting RD,
placing data on the AD bus, and asserting WR and CS. Data is sampled when WR or CS is deasserted.
Signal Description
"Utopia Receive Cell Available. "1" indicates that the receive FIFO contains a complete cell. "0" indicates that it does not.
Utopia Receive Clock. This is a free running clock input.
Utopia Receive Data. When one of the four ports is selected, the 77V126L200 transfers received cells to an ATM device
across this bus. Also see RXPARITY.
Utopia Receive Enable. Driven by an ATM device to indicate its ability to receive data across the RXDATA bus.
Utopia Receive Data Parity. Odd parity over RXDATA[7:0].
"Utopia Transmit Cell Available. "1" indicates that the transmit FIFO has room available for at least one complete cell. "0"
indicates that it does not.
Utopia Transmit Clock. This is a free running clock input.
Utopia Transmit Data. An ATM device transfers cells across this bus to the 77V126L200 for transmission. Also see TXPAR-
ITY.
Utopia Transmit Enable. Driven by an ATM device to indicate it is transmitting data across the TXDATA bus.
Utopia Transmit Data Parity. Odd parity across TXDATA[7:0]. Parity is checked and errors are indicated in the Interrupt Sta-
tus Registers, as enabled in the Master Control Register. No other action is taken in the event of an error. Tie high or low if
unused.
Table 2 Signal Descriptions (Part 1 of 2)
Utopia Bus Signals
Utility Bus Signals
Line Side Signals
4 of 30
December 2004