IDT77V126L200TFI8 IDT, Integrated Device Technology Inc, IDT77V126L200TFI8 Datasheet - Page 28

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IDT77V126L200TFI8

Manufacturer Part Number
IDT77V126L200TFI8
Description
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet

Specifications of IDT77V126L200TFI8

Number Of Channels
1
Type Of Atm Phy Interface
UTOPIA
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (min)
3V
Operating Supply Voltage (max)
3.6V
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Pin Count
64
Mounting
Surface Mount
Lead Free Status / RoHS Status
Not Compliant
OSC, TXREF and Reset Timing
AC Test Conditions
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
IDT77V126L200
Note: The minimum RESET Pulse Width is either two RxCLK cycles, two TxCLK cycles, or two OSC cycles, whichever is greater (and
applicable).
Tcyc
Tckh
Tckl
Tcc
Ttrh
Ttrl
Trspw
Trrpw
Symbol
OSC cycle period (25.6 Mbps)
(51.2 Mbps)
OSC high time
OSC cycle to cycle period variation
TXREF High Time
TXREF Low Time
Minimum RST Pulse Width
RXREF Pulse Width (For default setting in register 0x03 and 25.6
Mbps. Can be programmed for multiples of this amount.)
OSC low time
GND to 3.0V
3ns
1.5V
1.5V
See Figure 22
TXREF
RXREF
OSC
RST
Parameter
Tcyc
Figure 21 OSC, TXREF and Reset Timing
Trspw
* Includes jig and scope capacitances.
28 of 30
Trrpw
Ttrl
D.U.T.
Tckh
Figure 22 Output Load
Tckl
30
15
40
40
35
35
two OSC cycles
0.9
900
Ttrh
Min
3505 drw 45
3.3V
31.25
15.625
1
(31.25ns)
Typ
.
1.2K
30pF*
33
16.5
60
60
1
1.1
Max
December 2004
ns
ns
%
%
%
ns
ns
Receive
Data Bit
Period
Unit

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