PXB4219EV34NP Infineon Technologies, PXB4219EV34NP Datasheet - Page 71

• Manufacturer Part Number: PXB4219EV34NP
• Manufacturer: Infineon Technologies

Specifications of PXB4219EV34NP

• Data Rate: 2.048Mbps
• Number Of Channels: 1
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Transmit
Receive
Figure 19
4.5.1
In transmit direction the ICRC generates RTS values for each port independently and
writes them into the RTS Transmit FIFO.
Received RTS values are written to the port specific RTS Receive FIFO to compensate
cell delay variation. RTS values for each port are processed at a frequency equal to the
SRTS period (8 cells). ACM values are processed immediately by the corresponding
PLL.
4.5.2
This block generates 32-bit control frames that are used for communication with the rest
of the system.
For synchronization with the system the received synchronization signal PDSYN is used.
However, if this signal can’t be extracted from the received bit stream by the frame
receiver, the frames are generated by means of an internal synchronization counter.
The frame output is put in tristate during power down of the internal interface. As soon
as the internal synchronization counter is synchronized on PDSYN signal, the frame
output is enabled.
Data Sheet
Clock
Clock
Line
Line
lc8
1
0
Microprocessor Interface, Test and Control
Data Flow
Frame Generator
PLL
lgc
FILTER
0
1
32.768 MHz
Block Diagram of the ICRC
PLL
2.43 MHz
generation
SRTS
ACM
RTS
PLL
PLL
Loopback 1
ena
Receive
0
1
FIFO
RTS
RTS
rtsi
rtso
lgs
ena
1
0
0
1
71
lpcr
0
1
PXB 4219E, PXB 4220E, PXB 4221E
Buffer Filling
Transmit
(ACM)
FIFO
2.43 MHz
RTS
RTS
Receiver 1
Receiver 2
Generator
Fractional
Divider
Frame
Frame
Frame
Operational Description
lptu
lptd
1
0
1
0
lprd
IWE8, V3.4
0
1
lpru
2003-01-20
0
1
Recovery
SDI
SDOR
PDSYN
SDOD
SCLK
CLK52
RFCLK
Interface
Clock
Bdoti