PSB50505EV13GXT Lantiq, PSB50505EV13GXT Datasheet - Page 16

• Manufacturer Part Number: PSB50505EV13GXT
• Manufacturer: Lantiq

Specifications of PSB50505EV13GXT

• Lead Free Status / RoHS Status: Supplier Unconfirmed

• IMA interface:
• 8 generic framer interfaces with integrated transmit clock selector supporting
• UTOPIA industry standard interface:
• 16-bit generic microprocessor interface for control and configuration of the chip runs
• External synchronous Flow-Through SSRAM 1 x 64k x 33 bit or 1 x 64k x 32 bit
• Build-in data path loops for test
• Cell insertion/extraction via microprocessor interface
• 3.3 Volt power supply with 5 Volt tolerant inputs
• Typical power dissipation 1 Watt
• P-BGA-256 package
• Temperature range from -40° to +85°C
Data Sheet
– Internal clock recovery circuit using Synchronous Residual Time Stamp (SRTS, for
– Trunk freezing and conditioning according to Bellcore TR-NWT-000170 [14]
– Programmable threshold between read and write pointer of Mapping Buffer
– Output Signal for buffer threshold crossing
– Output Signal for discarded cell
– Output pins for port number indication
– Synchronous Mode (SYM) for E1
– Generic Interface Mode (GIM)
– FALC Mode (FAM): Glue-less interface for Infineon’s Framer and Line Interface
– Echo Canceller Mode (EC): ATM cells are duplicated internally and transmitted via
– Level 2 in slave mode; 8 data, 5 address lines
– Level 1 in master/slave mode
– UTOPIA clock up to 38.88 MHz
either in Intel 386EX or Motorola compatible mode
required
fully filled cells only) or Adaptive Clock Method (ACM) for unstructured CES ports.
For SRTS a patent fee needs to be paid. Optionally, it’s possible to order the PXB
4221 device, which comes without SRTS clock recovery.
Components (FALC)
two framer ports
16
PXB 4219E, PXB 4220E, PXB 4221E
IWE8, V3.4
2003-01-20
Overview