ICS8523BG IDT, Integrated Device Technology Inc, ICS8523BG Datasheet - Page 11

• Manufacturer Part Number: ICS8523BG
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Clock Driverr

Specifications of ICS8523BG

• Number Of Clock Inputs: 2
• Mode Of Operation: Differential
• Output Frequency: 650MHz
• Output Logic Level: HSTL
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.465V
• Package Type: TSSOP
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 20
• Lead Free Status / RoHS Status: Not Compliant

Recommendations for Unused Input and Output Pins
Inputs:
LVCMOS Control Pins:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
CLK/CLK I
For applications not requiring the use of the differential input, both
CLK and CLK can be left floating. Though not required, but for
additional protection, a 1kΩ resistor can be tied from CLK to
ground.
PCLK/PCLK I
For applications not requiring the use of a differential input, both
the PCLK and PCLK pins can be left floating. Though not required,
but for additional protection, a 1kΩ resistor can be tied from PCLK
to ground.
Schematic Example
Figure 5 shows a schematic example of the ICS8523. In this
example, the input is driven by an IDT HiPerClockS HSTL driver.
The decoupling capacitors should be physically located near the
Figure 5. ICS8523 HSTL Buffer Schematic Example
IDT™ / ICS™ HSTL FANOUT BUFFER
ICS8523
LOW SKEW, 1-TO-4, DIFFERENTIAL-TO-HSTL FANOUT BUFFER
1.8V
LVHSTL Driver
Zo = 50 Ohm
Zo = 50 Ohm
NPUT
NPUT
:
R9
50
:
R10
50
R11
1K
R12
1K
3.3V
3.3V
C1
0.1u
8523
10
1
2
3
4
5
6
7
8
9
U3
GND
CLK_EN
CLK_SEL
CLK
nCLK
PCLK
nPCLK
NC
NC
VDD
1.8V
C2
0.1u
C3
0.1u
VDDO
VDDO
nQ0
nQ1
nQ2
nQ3
Q0
Q1
Q2
Q3
20
19
18
17
16
15
14
13
12
11
1.8V
1.8V
11
Outputs:
HSTL Outputs
All unused LVHSTL outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential output
pair should either be left floating or terminated.
power pin. For ICS8523, the unused clock outputs can be left
floating.
Zo = 50
Zo = 50
Zo = 50
Zo = 50
Zo = 50
Zo = 50
Zo = 50
Zo = 50
R6
50
R8
50
R2
50
R4
50
R5
50
R7
50
R1
50
R3
50
+
-
+
-
+
-
+
-
ICS8523CGREV. D MARCH 13, 2007