71M6541F-DB Maxim Integrated Products, 71M6541F-DB Datasheet - Page 98

• Manufacturer Part Number: 71M6541F-DB
• Description: Power Management Modules & Development Tools 71M6541 Eval Kit
• Manufacturer: Maxim Integrated Products

Specifications of 71M6541F-DB

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

thus provides a suitable implementation of temperature compensation, but other methods are possible in
MPU firmware by utilizing the on-chip temperature sensors and the CE RAM GAIN_ADJn storage locations.
The demonstration code maintains three separate sets of PPMC and PPMC2 coefficients and computes
three separate GAIN_ADJn values based on the sensed temperature using the equation below:
temperature is 27
•
4.7.3 Temperature Compensation for VREF with Local Sensors
This section discusses metrology temperature compensation for the meter designs where local sensors
are used, as shown in
In these configurations where all sensors are directly connected to the 71M654x, each sensor channel’s
accuracy is affected by the voltage variation in the 71M654x VREF due to temperature. The VREF in the
71M654x can be compensated digitally using a second-order polynomial function of temperature. The
71M654x features an on-chip temperature sensor for the purpose of temperature compensating its VREF.
There are also error sources external to the 71M654x. The voltage sensor resistor dividers and the shunt
current sensor and/or CT and their corresponding signal conditioning circuits also have a temperature
dependency, which also may require compensation, depending on the required accuracy class. The
compensation for these external error sources may be optionally lumped with the compensation for VREF by
incorporating their compensation into the PPMC and PPMC2 coefficients for each corresponding channel.
The MPU has the responsibility of computing the necessary compensation values required for each sensor
channel based on the sensed temperature. Teridian provides demonstration code that implements the
GAIN_ADJn compensation equation shown below. The resulting GAIN_ADJn values are stored by the
MPU in three CE RAM locations GAIN_ADJ0-GAIN_ADJ2 (CE RAM 0x40-0x42). The demonstration code
Where, TEMP_X is the deviation from nominal or calibration temperature expressed in multiples of
0.1 °C. For example, since the 71M654x calibration (reference) temperature is 22
from 22
Table 73
for which they compensate.
•
•
In the demonstration code, temperature compensation behavior is determined by the values stored in the
PPMC and PPMC2 coefficients for each of the three channels, which are setup by the MPU demo code at
initialization time from values that are previously stored in EEPROM.
To disable temperature compensation in the demonstration code, PPMC and PPMC2 are both set to zero
for each of the three GAIN_ADJn channels. To enable temperature compensation, the PPMC and PPMC2
coefficients are set with values that match the expected temperature variation of each corresponding
sensor channel.
98
GAIN_ADJ0 compensates for the VA and VB (71M6542F only) voltage measurements in the 71M654x
and is used to compensate the VREF in the 71M654x. The designer may optionally add
compensation for the resistive voltage dividers into the PPMC and PPMC2 coefficients for this
channel.
GAIN_ADJ1 provides compensation for the IA current channel and compensates for the 71M654x
VREF. The designer may optionally add compensation for the shunt or CT and its corresponding
signal conditioning circuit into the PPMC and PPMC2 coefficients for this channel.
GAIN_ADJ2 provides compensation for the IB current channel and compensates for the 71M654x VREF.
The designer may optionally add compensation for the CT and its signal conditioning circuit into the
PPMC and PPMC2 coefficients for this channel.
o
Gain Adjustment Output
C.
shows the three GAIN_ADJn equation output values and the voltage or current measurements
GAIN_ADJ0
GAIN_ADJ1
GAIN_ADJ2
o
C, then TEMP_X = (27-22) x 10 = 50 (decimal), which represents a +5
GAIN
Figure 35
_
© 2008–2011 Teridian Semiconductor Corporation
ADJ
Table 72: GAIN_ADJn Compensation Channels
=
and
16385
Figure
CE RAM Address
+
10
⋅
TEMP
37.
0x40
0x41
0x42
2
_
14
X
⋅
PPMC
+
71M6541D/F
100
⋅
TEMP
VA
IA
IB
2
_
23
X
2
⋅
PPMC
o
71M6542F
C and the measured
2
VA, VB
IA
IB
o
C deviation
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