71M6541F-DB Maxim Integrated Products, 71M6541F-DB Datasheet - Page 36

• Manufacturer Part Number: 71M6541F-DB
• Description: Power Management Modules & Development Tools 71M6541 Eval Kit
• Manufacturer: Maxim Integrated Products

Specifications of 71M6541F-DB

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

follows:
Ports P0-P3 on the chip are bi-directional and control SEGDIO0-15. Each port consists of a Latch (SFR
P0 to P3), an output driver and an input buffer, therefore the MPU can output or read data through any of
these ports. Even if a DIO pin is configured as an output, the state of the pin can still be read by the
MPU, for example when counting pulses issued via DIO pins that are under CE control.
Clock Stretching (CKCON)
The three low order bits of the CKCON[2:0] (SFR 0x8E) register define the stretch memory cycles that
are used for MOVX instructions when accessing external peripherals. The practical value of this register
for the 71M6541D/F and 71M6542F is to guarantee access to XRAM between CE, MPU, and SPI. The
default setting of CKCON[2:0] (001) should not be changed.
Table 16
from 0 to 7. The widths of the signals are counted in MPU clock cycles. The post-reset state of the
CKCON[2:0] (001), which is shown in bold in the table, performs the MOVX instructions with a stretch
value equal to 1.
2.4.4 Instruction Set
All instructions of the generic 8051 microcontroller are supported. A complete list of the instruction set
and of the associated op-codes is contained in the 71M654X Software User’s Guide (SUG).
2.4.5 UARTs
The 71M6541D/F and 71M6542F include a UART (UART0) that can be programmed to communicate
with a variety of AMR modules and other external devices. A second UART (UART1) is connected to the
optical port, as described in
The UARTs are dedicated 2-wire serial interfaces, which can communicate with an external host processor
at up to 38,400 bits/s (with MPU clock = 1.2288 MHz). The operation of the RX and TX UART0 pins is as
36
At power-up SEGDIO0-15 are configured as inputs. It is necessary to write PORT_E = 1 (I/O RAM
0x270C[5]) to enable SEGDIO0-15. The default PORT_E = 0 blocks any momentary output
transient pulses that would otherwise occur when SEGDIO0-15 are reset on power-up.
Name
SFR
shows how the signals of the External Memory Interface change when stretch values are set
P0
P1
P2
P3
CKCON[2:0]
000
001
010
011
100
101
110
111
Address
0xA0
0xB0
0x80
0x90
SFR
© 2008–2011 Teridian Semiconductor Corporation
2.5.7 UART and Optical
Stretch
Table 15: Port Registers (SEGDIO0-15)
Table 16: Stretch Memory Cycle Width
Value
0
1
2
3
4
5
6
7
D7
DIO_DIR[15:12]
memaddr
DIO_DIR[11:8]
DIO_DIR[3:0]
DIO_DIR[7:4]
Read Signal Width
D6
1
2
3
4
5
6
7
8
Interface.
D5
memrd
1
2
3
4
5
6
7
8
D4
memaddr
Write Signal Width
D3
2
3
4
5
6
7
8
9
D2
DIO[15:11]
DIO[11:8]
DIO[3:0]
DIO[7:4]
memwr
1
1
2
3
4
5
6
7
D1
D0
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