MAX2063ETM+T Maxim Integrated Products, MAX2063ETM+T Datasheet - Page 14

• Manufacturer Part Number: MAX2063ETM+T
• Description: RF Amplifier Dual, 50MHz to 1000M Hz High-Linearity, S
• Manufacturer: Maxim Integrated Products

Specifications of MAX2063ETM+T

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Dual 50MHz to 1000MHz High-Linearity,
Serial/Parallel-Controlled Digital VGA
14
PIN
10
11
14
15
16
17
18
19
21
24
26
27
29
30
31
32
34
35
37
42
43
44
45
46
47
—
8
9
D_ATT_OUT_2
D_ATT_OUT_1
AMP_OUT_2
AMP_OUT_1
D_ATT_IN_2
V
V
AMP_IN_2
REG_OUT
AMP_IN_1
STA_B_2
STA_A_2
CC_AMP_2
AMPSET
CC_AMP_1
V
DA_SP
NAME
CC_RG
D0_2
D1_2
D2_2
D3_2
D4_2
PD_2
PD_1
D4_1
D3_1
D2_1
D1_1
D0_1
EP
Regulator Supply Input. Connect to a 3.3V or 5V external power supply. V
circuits except for the driver amplifiers. Bypass with a 10nF capacitor as close as possible to
the pin.
Digital Attenuator Preprogrammed Attenuation-State Logic Input, Path 2
5-Bit Digital Attenuator RF Input (50I), Path 2. Requires a DC-blocking capacitor.
1dB Attenuator Logic Input, Path 2. Logic 0 = disable, Logic 1 = enable
2dB Attenuator Logic Input, Path 2. Logic 0 = disable, Logic 1 = enable
4dB Attenuator Logic Input, Path 2. Logic 0 = disable, Logic 1 = enable
8dB Attenuator Logic Input, Path 2. Logic 0 = disable, Logic 1 = enable
5-Bit Digital Attenuator Output (50I), Path 2. Requires a DC-blocking capacitor. Connect to
AMP_IN_2 through a 1000pF capacitor.
16dB Attenuator Logic Input, Path 2. Logic 0 = disable, Logic 1 = enable.
Digital Attenuator Serial/Parallel Control Select. Set DA_SP to 1 to select serial control. Set
DA_SP to 0 to select parallel control.
Driver Amplifier Supply Voltage Input, Path 2. Bypass with a 10nF capacitor as close as
possible to the pin.
Driver Amplifier Input (50I), Path 2. Connect to D_ATT_OUT_2 through a 1000pF capacitor.
Power-Down, Path 2. See Table 2 for operation details.
Driver Amplifier Output (50I), Path 2. Connect a pullup inductor from AMP_OUT_2 to V
Regulator Output. Bypass with a 1FF capacitor.
Driver Amplifier Bias Setting for 3.3V Operation. Set to logic 1 for 3.3V on pins V
V
Driver Amplifier Output (50I), Path 1. Connect a pullup inductor from AMP_OUT_1 to V
Power-Down, Path 1. See Table 2 for operation details.
Driver Amplifier Input (50I), Path 1. Connect to D_ATT_OUT_1 through a 1000pF capacitor.
Driver Amplifier Supply Voltage Input, Path 1. Bypass with a 10nF capacitor as close as
possible to the pin.
16dB Attenuator Logic Input, Path 1. Logic 0 = disable, Logic 1 = enable.
5-Bit Digital Attenuator Output (50I), Path 1. Requires a DC-blocking capacitor. Connect to
AMP_IN_1 through a 1000pF capacitor.
8dB Attenuator Logic Input, Path 1. Logic 0 = disable, Logic 1 = enable.
4dB Attenuator Logic Input, Path 1. Logic 0 = disable, Logic 1 = enable.
2dB Attenuator Logic Input, Path 1. Logic 0 = disable, Logic 1 = enable.
1dB Attenuator Logic Input, Path 1. Logic 0 = disable, Logic 1 = enable.
Exposed Pad. Internally connected to GND. Connect to a large PCB ground plane for proper
RF performance and enhanced thermal dissipation.
CC_AMP2
State A
Logic = 0
Logic = 1
Logic = 0
Logic = 1
. Set to logic 0 for 5V.
State B
Logic = 0
Logic = 0
Logic = 1
Logic = 1
Digital Attenuator 2
Preprogrammed State 1
Preprogrammed State 2
Preprogrammed State 3
Preprogrammed State 4
FUNCTION
Pin Description (continued)
CC_RG
CC_AMP1
powers all
CC_
CC_
and
.
.