MAX1385BUTM+ Maxim Integrated Products, MAX1385BUTM+ Datasheet - Page 33

• Manufacturer Part Number: MAX1385BUTM+
• Description: RF Wireless Misc IC RF LDMOS BIAS CNTRLR
• Manufacturer: Maxim Integrated Products

Specifications of MAX1385BUTM+

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The Hardware Alarm Configuration register controls
SAFE1, SAFE2, and ALARM outputs. Write to the
Hardware Alarm Configuration register by sending the
appropriate write command byte followed by data bits
D15–D0 (see Table 15). Bits D15–D8 are don’t care.
Read the Hardware Alarm Configuration register by
sending the appropriate read command byte.
Set SETSAFE1 to 1 to immediately force SAFE1 active.
This is especially useful when SAFE1 is connected to
OPSAFE1, giving the user software control over shut-
ting down the LDMOS transistor. Set SETSAFE1 to 0 for
normal operation. SETSAFE2 has the same functionality
as SETSAFE1 but for channel 2.
Set ALARMPOL to 1 to configure ALARM active-low. Set
it to 0 to configure ALARM active-high. Set ALARMOPN
to 1 to configure ALARM open-drain. Set it to 0 to config-
ure ALARM push-pull. Set SAFE1POL to 1 to configure
SAFE1 for active-low, and to 0 for active-high. Set
SAFE2POL to 1 to configure SAFE2 for active-low, and to
0 for active-high. Set SAFE1OPN to 1 to configure SAFE1
for open-drain, and to 0 for push-pull. Set SAFE2OPN
to 1 to configure SAFE2 for open-drain, and to 0 for
push-pull.
When connecting SAFE1 and SAFE2 outputs to
OPSAFE1 and OPSAFE2 inputs, configure the device
as follows:
1) Set SAFE1POL and SAFE2POL to 0s.
Table 10. LOWIPE1 and LOWIPE2 (Read/Write)
Table 12. PGACAL (Write)
RESERVED
BIT NAME
SELFTIME
BIT NAME
DOCAL
FIRSTB
LCAL
X
—
—
DATA BIT
D15–D8
D7–D3
DATA BIT
D2
D1
D0
D14–D8
D7–D0
______________________________________________________________________________________
D15
RESET STATE
0000 0000
ALMHCFG (Read/Write)
0
X
0
0
0
POR
X
1
Dual RF LDMOS Bias Controllers
Reserved. Set to 0.
Don’t care.
1 = Tracking calibration mode.
0 = Acquisition calibration mode.
1 = Initiate the calibration defined by FIRSTB (one time).
0 = Do not initiate a calibration.
1 = Initiate periodic calibrations defined by FIRSTB (every 15ms).
0 = Stop periodic calibrations.
1 = Low wiper autocalibration.
0 = No low wiper autocalibration.
Don’t care.
8-bit coarse low wiper DAC input code. D7 is the MSB.
2) Set SAFE1OPN and SAFE2OPN to 0s.
This ensures that when SAFE1 and SAFE2 are assert-
ed, and connected to OPSAFE1 and OPSAFE2, the
LDMOS transistors are shut off.
The Analog-to-Digital Conversion register selects which
inputs to the ADC are converted. Write to the Analog-to-
Digital Conversion register by sending the appropriate
write command byte followed by data bits D15–D0 (see
Table 16). Bits D15–D12 are don’t care. Bits D11–D8
are reserved bits and need to be set to 0. Read the
results of the conversions in the FIFO by sending the
appropriate read command byte. See the ADC
Description section for a complete description of the
ADC.
Set CONCONV to 1 to convert selected inputs to the
ADC continuously and to 0 to convert selected inputs to
the ADC only once. Set ADCSEL2 to 1 to select volt-
ages at ADCIN2 to be converted. Set IEXT2 to 1 to
select voltages at PGAOUT2 to be converted. Set
Table 11. FINECAL1 and FINECAL2 (Write)
with I
DATA BIT
D15–D10
D9–D0
FUNCTION
FUNCTION
2
00 0000 0000
C/SPI Interface
POR
X
Don’t care.
10-bit fine DAC input code.
D9 is the MSB.
FUNCTION
ADCCON (Write)
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