MAX1385BUTM+ Maxim Integrated Products, MAX1385BUTM+ Datasheet - Page 30

• Manufacturer Part Number: MAX1385BUTM+
• Description: RF Wireless Misc IC RF LDMOS BIAS CNTRLR
• Manufacturer: Maxim Integrated Products

Specifications of MAX1385BUTM+

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Dual RF LDMOS Bias Controllers
with I
Alarm Modes section). Setting ALARMCMP does not
affect SAFE1 and SAFE2 outputs. Program
ALARMHYST1 and ALARMHYST0 to set the amount of
built-in hysteresis used in window-threshold mode.
See the ALARM Output and SAFE1/SAFE2 Outputs
sections for a description of the relationship between
ALARM and SAFE1 and SAFE2. Set TALARM2 to 1 to
allow channel 2 temperature measurements to control
the state of SAFE2 and ALARM based on channel 2
temperature thresholds. Set TWIN2 to 0 to enable hys-
teresis-threshold mode and to 1 to enable window-
threshold mode for channel 2 temperature
measurements (see the Alarm Modes section). Set
IALARM2 to 1 to allow channel 2 current measurements
to control the state of SAFE2 and ALARM based on
channel 2 current thresholds. Set IWIN2 to 0 to enable
hysteresis-threshold mode and to 1 to enable window-
threshold mode for channel 2 current measurements.
Set TALARM1 to 1 to allow channel 1 temperature mea-
surements to control the state of SAFE1 and ALARM
based on channel 1 temperature thresholds. Set TWIN1
to 0 to enable hysteresis-threshold mode and to 1 to
enable window-threshold mode for channel 1 tempera-
ture measurements (see the Alarm Modes section). Set
IALARM1 to 1 to allow channel 1 current measurements
to control the state of SAFE1 and ALARM based on
channel 1 current thresholds. Set IWIN1 to 0 to enable
hysteresis-threshold mode and to 1 to enable window-
threshold mode for channel 1 current measurements.
Write to the Coarse DAC1/DAC2 High Wiper Input reg-
ister by sending the appropriate write command byte
Table 7. DCFIG (Read/Write)
30
BIT NAME
REFADC1
REFADC0
REFDAC1
REFDAC0
PG2SET1
PG2SET0
PG1SET1
PG1SET0
CKSEL1
CKSEL0
______________________________________________________________________________________
X
2
DATA BIT
D15–D10
C/SPI Interface
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
HIWIPE1 and HIWIPE2 (Read/Write)
POR
X
0
0
0
0
0
0
0
0
0
0
Don’t care
PGA 2 gain-setting
PGA 2 gain-setting
PGA 1 gain-setting
PGA 1 gain-setting
Clock mode and CNVST
configuration
Clock mode and CNVST
configuration
ADC reference select
ADC reference select
DAC reference select
DAC reference select
FUNCTION
followed by data bits D15–D0 (see Table 9). Bits
D14–D8 are don’t care. Read the Coarse DAC1/DAC2
High Wiper Input register by sending the appropriate
read command byte. The DAC output is not updated
until an LDAC command is issued, at which point the
Table 7a. Gain-Setting Modes
X = Don’t care.
Table 7b. Clock Modes
Table 7c. ADC Reference Selection
X = Don’t care.
CKSEL1 CKSEL0
REFADC1
PG_SET1
0
0
1
1
0
1
1
0
0
1
REFADC0
0
1
0
1
PG_SET0
X
0
1
0
1
X
CONVERSION
CLOCK
Internal
Internal
Internal
External. Bypass REFADC with a
0.1µF capacitor to AGND.
Internal. Leave REFADC
unconnected.
Internal. Connect a 0.1µF capacitor
to REFADC for better noise
performance.
—
PGA_ gain of 2
PGA_ gain of 10
PGA_ gain of 25
DESCRIPTION
Internally timed
acquisitions and
conversions.
Conversions started by
a write to the Analog-
to-Digital Conversion
register or setting the
CONCONV bit.
Internally timed
acquisitions and
conversions.
Conversions begin with
a high-to-low transition
at CNVST.
Reserved. Do not use.
Externally timed
acquisitions by
CNVST. Conversions
internally timed.
FUNCTION
ACQUISITION/
SAMPLING