XC2S300E-6PQG208C Xilinx Inc, XC2S300E-6PQG208C Datasheet - Page 35

• Manufacturer Part Number: XC2S300E-6PQG208C
• Description: FPGA Spartan®-IIE Family 300K Gates 6912 Cells 357MHz 0.15um Technology 1.8V 208-Pin PQFP
• Manufacturer: Xilinx Inc
• Series: Spartan™-IIEr

Specifications of XC2S300E-6PQG208C

• Package: 208PQFP
• Family Name: Spartan®-IIE
• Device Logic Cells: 6912
• Device Logic Units: 1536
• Device System Gates: 300000
• Maximum Internal Frequency: 357 MHz
• Typical Operating Supply Voltage: 1.8 V
• Maximum Number Of User I/os: 146
• Ram Bits: 65536
• Number Of Logic Elements/cells: 6912
• Number Of Labs/clbs: 1536
• Total Ram Bits: 65536
• Number Of I /o: 146
• Number Of Gates: 300000
• Voltage - Supply: 1.71 V ~ 1.89 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 208-BFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1326

Switching Characteristics
Internal timing parameters are derived from measuring
internal test patterns. Listed below are representative val-
ues. For more specific, more precise, and worst-case guar-
anteed data, use the values reported by the static timing
analyzer (TRACE in the Xilinx Development System) and
Global Clock Input to Output Delay for LVTTL, with DLL (Pin-to-Pin)
Global Clock Input to Output Delay for LVTTL, without DLL (Pin-to-Pin)
DS077-3 (v2.3) June 18, 2008
Product Specification
Notes:
1.
2.
3.
4.
Notes:
1.
2.
3.
Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and
where all accessible IOB and CLB flip-flops are clocked by the global clock net.
Output timing is measured at 1.4V with 35 pF external capacitive load for LVTTL. The 35 pF load does not apply to the Min values.
For other I/O standards and different loads, see the tables
page
DLL output jitter is already included in the timing calculation.
For data output with different standards, adjust delays with the values shown in
Standards(1), page
Global Clock Input Adjustments, page
Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and
where all accessible IOB and CLB flip-flops are clocked by the global clock net.
Output timing is measured at 1.4V with 35 pF external capacitive load for LVTTL. The 35 pF load does not apply to the Min values.
For other I/O standards and different loads, see the tables
page
For data output with different standards, adjust delays with the values shown in
Standards(1), page
Global Clock Input Adjustments, page
T
Symbol
Symbol
ICKOFDLL
T
ICKOF
41.
41.
R
LVTTL global clock input to output delay using
output flip-flop for LVTTL, 12 mA, fast slew rate,
with DLL.
LVTTL global clock input to output
delay using output flip-flop for
LVTTL, 12 mA, fast slew rate,
without DLL.
40. For a global clock input with standards other than LVTTL, adjust delays with values from the
40. For a global clock input with standards other than LVTTL, adjust delays with values from the
Description
Description
42.
42.
www.xilinx.com
Constants for Calculating TIOOP
Constants for Calculating TIOOP
Spartan-IIE FPGA Family: DC and Switching Characteristics
XC2S100E
XC2S150E
XC2S200E
XC2S300E
XC2S400E
XC2S600E
XC2S50E
back-annotated to the simulation netlist. All timing parame-
ters assume worst-case operating conditions (supply volt-
age and junction temperature). Values apply to all
Spartan-IIE devices unless otherwise noted.
Device
Min
1.0
All
IOB Output Delay Adjustments for Different
IOB Output Delay Adjustments for Different
Min
1.5
1.5
1.5
1.5
1.5
1.5
1.6
All
Speed Grade
(1)
and
and
Speed Grade
Max
3.1
-7
Delay Measurement Methodology,
Delay Measurement Methodology,
(1)
Max
4.4
4.4
4.5
4.5
4.5
4.6
4.7
-7
Max
3.1
-6
Max
4.6
4.6
4.7
4.7
4.7
4.8
4.9
-6
I/O Standard
I/O Standard
Units
Units
ns
ns
ns
ns
ns
ns
ns
ns
35