74LVC74APW-T NXP Semiconductors, 74LVC74APW-T Datasheet - Page 13

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74LVC74APW-T

Manufacturer Part Number
74LVC74APW-T
Description
Flip Flop D-Type Pos-Edge 2-Element 14-Pin TSSOP T/R
Manufacturer
NXP Semiconductors
Datasheet

Specifications of 74LVC74APW-T

Package
14TSSOP
Logic Function
D-Type
Logic Family
LVC
Number Of Element Outputs
1
Number Of Elements Per Chip
2
Input Signal Type
Single-Ended
Output Signal Type
Differential
Set/reset
Set/Reset
Typical Operating Supply Voltage
1.8|2.5|3.3 V
Operating Temperature
-40 to 125 °C
NXP Semiconductors
Fig 13. Package outline SOT762-1 (DHVQFN14)
74LVC74A_6
Product data sheet
DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
14 terminals; body 2.5 x 3 x 0.85 mm
DIMENSIONS (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
UNIT
mm
VERSION
OUTLINE
SOT762-1
max.
A
1
(1)
terminal 1
index area
0.05
0.00
A 1
terminal 1
index area
E h
L
0.30
0.18
14
1
b
IEC
- - -
0.2
2
c
13
e
D
3.1
2.9
0
(1)
1.65
1.35
D h
e 1
D h
D
MO-241
JEDEC
E
2.6
2.4
(1)
b
REFERENCES
Rev. 06 — 4 June 2007
1.15
0.85
Dual D-type flip-flop with set and reset; positive-edge trigger
E h
9
6
0.5
e
7
8
JEITA
B
- - -
e
scale
w
v
2.5
e 1
2
M
M
A
E
C
C
0.5
0.3
A
L
B
0.1
v
0.05
w
y 1 C
A
A 1
0.05
y
PROJECTION
EUROPEAN
5 mm
0.1
y 1
detail X
74LVC74A
X
C
© NXP B.V. 2007. All rights reserved.
y
ISSUE DATE
02-10-17
03-01-27
c
SOT762-1
13 of 16

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