74LVC74APW-T NXP Semiconductors, 74LVC74APW-T Datasheet - Page 10

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74LVC74APW-T

Manufacturer Part Number
74LVC74APW-T
Description
Flip Flop D-Type Pos-Edge 2-Element 14-Pin TSSOP T/R
Manufacturer
NXP Semiconductors
Datasheet

Specifications of 74LVC74APW-T

Package
14TSSOP
Logic Function
D-Type
Logic Family
LVC
Number Of Element Outputs
1
Number Of Elements Per Chip
2
Input Signal Type
Single-Ended
Output Signal Type
Differential
Set/reset
Set/Reset
Typical Operating Supply Voltage
1.8|2.5|3.3 V
Operating Temperature
-40 to 125 °C
NXP Semiconductors
12. Package outline
Fig 10. Package outline SOT108-1 (SO14)
74LVC74A_6
Product data sheet
SO14: plastic small outline package; 14 leads; body width 3.9 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
inches
UNIT
mm
OUTLINE
VERSION
SOT108-1
0.069
max.
1.75
A
0.010
0.004
0.25
0.10
A
14
1
1
Z
pin 1 index
y
0.057
0.049
1.45
1.25
A
2
076E06
IEC
0.01
0.25
e
A
3
0.019
0.014
0.49
0.36
b
p
D
0.0100
0.0075
0.25
0.19
MS-012
JEDEC
c
REFERENCES
8.75
8.55
0.35
0.34
D
(1)
0
Rev. 06 — 4 June 2007
Dual D-type flip-flop with set and reset; positive-edge trigger
0.16
0.15
E
4.0
3.8
b
(1)
p
8
7
JEITA
scale
1.27
0.05
2.5
e
w
M
c
0.244
0.228
H
6.2
5.8
E
A
2
0.041
5 mm
1.05
A
L
1
0.039
0.016
1.0
0.4
L
p
H
E
E
detail X
0.028
0.024
0.7
0.6
Q
L
PROJECTION
L
EUROPEAN
0.25
0.01
p
Q
v
(A )
3
0.25
0.01
A
w
74LVC74A
0.004
A
0.1
© NXP B.V. 2007. All rights reserved.
v
X
y
M
ISSUE DATE
99-12-27
03-02-19
A
0.028
0.012
Z
0.7
0.3
(1)
SOT108-1
8
0
o
o
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