821054PQF Integrated Device Technology (Idt), 821054PQF Datasheet - Page 15

• Manufacturer Part Number: 821054PQF
• Description: Audio Codec 4ADC / 4DAC 64-Pin PQFP
• Manufacturer: Integrated Device Technology (Idt)
• Type: PCMr

Specifications of 821054PQF

• Package: 64PQFP
• Number Of Channels: 4ADC /4 DAC
• Number Of Dacs: 4
• Operating Supply Voltage: 5 V

IDT821054 QUAD PROGRAMMABLE PCM CODEC WITH MPI INTERFACE
2.10
channels. The level meter is designed to emulate the off-chip PCM test
equipment so as to facilitate the line-card, subscriber line and users
telephone set monitoring. The level meter tests the return signal and
reports the measurement result via the MPI interface. When combined
with tone generation and loopbacks, it allows the microprocessor to test
the channel integrity. The signal on the channel selected by the CS[1:0]
bits in GREG21 will be metered.
level meter counter register (GREG20) is used to set the value of time
cycles for sampling the PCM data (8 kHz sampling rate). The output of
level meter is sent to the level meter result registers GREG18 and
The IDT821054 integrates a level meter which is shared by all 4
The level meter is enabled by setting the LMO bit in GREG21 to ‘1’. A
LEVEL METERING
N
N
In GREG17:
Set FCS[2:0] bits to select FSK channel
Set BS bit to select specification (Bellcore or BT)
Set MAS = 0
Set FS = 1
Write message data into FSK-RAM
Set "Seizure Length" in GREG15
Total message data ≤ 64 bytes ?
Read FO and FS bit in GREG17
Set "Mark Length" in GREG16
Set "Data Length" in GREG14
Set "Flag Length" in GREG13
Finish sending message data ?
GREG17: FO = 0
Figure - 7 A Recommended Procedure of Programming the FSK Generator
FO = 1 ?
FS = 0 ?
Y
Y
Y
Y
Start
End
N
Set FO = 1
N
In GREG17:
Set FCS[2:0] bits to select FSK channel
Set BS bit to select specification (Bellcore or BT)
Set MAS = 1
Set FS = 1
GREG14: Set "Data Length" at this time
15
Finish sending all the message data ?
Write message data to be sent at this
GREG19. The LVLL[7:0] bits in GREG18 contain the lower 7 bits of the
result and a data-ready bit (LVLL[0]), while the LVLH[7:0] bits in
GREG19 contain the higher 8 bits of the result. An internal accumulator
sums the rectified samples until the value set in GREG20 is reached. By
then, the LVLL[0] bit is set to ‘1’ and accumulation result is latched into
GREG18 and GREG19 simultaneously.
GREG18 will be reset. It will be set to ‘1’ again by a new data available.
The contents of GREG18 and GREG19 will be overwritten by the
following metering result if they have not been read out yet. To read the
level meter result registers, it is recommended to read GREG18 (lower
byte of result) first.
the L/C bit is ‘1’, it means that metering mode is selected. In this mode,
GREG17: MAS = 0; FO = 0
Once the higher byte of result (GREG19) is read, the LVLL[0] bit in
The L/C bit in GREG21 determines the level meter operation mode. If
time to FSK-RAM
Y
End
INDUSTRIAL TEMPERATURE RANGE
GREG15: Set "Seizure Length" to 0
GREG16: Set "Mark Length" to 0
N