LE79R241DJC Zarlink, LE79R241DJC Datasheet - Page 9

• Manufacturer Part Number: LE79R241DJC
• Description: SLIC 1-CH 63dB 70mA 5V 32-Pin PLCC Tube
• Manufacturer: Zarlink

Specifications of LE79R241DJC

• Package: 32PLCC
• Number Of Channels Per Chip: 1
• Polarity Reversal: Yes
• Longitudinal Balanced: 63 dB
• Loop Current: 70(Min) mA
• Minimum Operating Supply Voltage: 4.75 V
• Typical Operating Supply Voltage: 5 V
• Typical Supply Current: 7.5 mA

PIN DESCRIPTIONS
AD, BD
BGND
CREF
GND
HPA, HPB
ILG
IMT
LD
P1–P3
R1
R2
R3
RSN
RSVD
RYE
SA, SB
TMP, TMN,
TMS
VBH
VBL
VCC
VLB
VREF
VSAB
VTX
Exposed
Pad
Pin Name
Output
Ground
+3.3 VDC
Ground
Output
Output
Output
Input
Input
Output
Output
Output
Input
Reserved
Output
Input
Output
Battery (Power)
Battery (Power)
+5 V Power Supply
Input
Input
Output
Output
Battery
Type
Provide the currents to the A and B leads of the subscriber loop.
Ground return for high and low battery supplies.
VCCD reference. It is the digital high logic supply rail, used by the Le79R241 ISLIC device
to codec interface.
Analog and digital ground return for VCC.
These pins connect to CHP, the external high-pass filter capacitor that separates the DC
loop-voltage from the voice transmission path.
ILG is proportional to the common-mode line current (IAD–IBD), except in disconnect
mode, where ILG is proportional to the current into grounded SB.
IMT is proportional to the differential line current (IAD + IBD), except in disconnect mode,
where IMT is proportional to the current into grounded SA. The Le79R241 ISLIC device
indicates thermal overload by pulling IMT to CREF.
The LD pin controls the input latch and responds to a 3-level input. When the LD pin is a
logic 1 (C
operate the mode-decoder. When the LD pin is a logic 0 (< 0.6), the logic levels on P1–P3
latch into the Am79241 control register bits that control the relay drivers (RD1–RD3). When
the LD pin level is at ~V
Inputs to the latch for the operating-mode decoder and the relay-drivers.
Collector connection for relay 1 driver. Emitter internally connected to BGND.
Collector connection for relay 2 driver. Emitter internally connected to RYE
Collector connection for relay 3 driver. Emitter internally connected to RYE.
The metallic current between AD and BD is equal to 500 times the current into this pin.
Networks that program receive gain and two-wire impedance connect to this node. This
input is at a virtual potential of VREF.
These pins are used during Zarlink testing. In the application, they must be left floating.
Emitter connection for R2 and R3. Normally connected to relay ground.
Sense the voltages on the line side of the fuse resistors at the A and B leads. External
sense resistors, RSA and RSB, protect these pins from lightning or power-cross.
External resistors connected from TMP to TMS and TMN to VBL to offload excess power
from the Le79R241 ISLIC device.
Connection to high-battery supply used for ringing and long loops. Connects to the
substrate. When only a single battery is available, it connects to both VBH and VBL.
Connection to low-battery supply used for short loops. When only a single battery is
available, this pin can be connected to VBH.
Positive supply for low voltage analog and digital circuits in the Le79R241 ISLIC device.
Sets the DC longitudinal voltage of the Le79R241 ISLIC device. It is the reference for the
longitudinal control loop. When the VLB pin is greater than VREF, the Le79R241 ISLIC
device sets the longitudinal voltage to a voltage approximately half-way between the
positive and negative power supply battery rails. When the VLB pin is driven to levels
between 0V and VREF, the longitudinal voltage decreases linearly with the voltage on the
VLB pin.
The VE790 series SLAC device provides this voltage which is used by the Le79R241 ISLIC
device for internal reference purposes. All analog input and output signals interfacing to the
VE790 series SLAC device are referenced to this pin.
Scaled-down version of the voltage between the sense points SA and SB on this pin.
The voltage between this pin and VREF is a scaled down version of the AC component of
the voltage sensed between the SA and SB pins. One end of the two-wire input impedance
programming network connects to VTX. The voltage at VTX swings positive and negative
with respect to VREF.
This must be electrically tied to VBH.
Zarlink Semiconductor Inc.
REF
− 1), the logic levels on P1–P3 latch into the Le79241 control register bits that
9
REF
± 0.3 V, the control register contents are locked.
Description