ISPGDX120A-5Q160 Lattice, ISPGDX120A-5Q160 Datasheet - Page 6

• Manufacturer Part Number: ISPGDX120A-5Q160
• Description: Analog & Digital Crosspoint ICs PROGRAMMABLE GEN DIG CROSSPOINT
• Manufacturer: Lattice

Specifications of ISPGDX120A-5Q160

• Mounting Style: SMD/SMT
• Number Of Arrays: 1
• Operating Supply Voltage: 5 V
• Supply Type: Single
• Configuration: 120 x 120
• Package / Case: TSSOP-24
• Input Level: TTL
• Output Level: TTL
• Supply Voltage (max): 5.25 V
• Supply Voltage (min): 4.75 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Product: Digital Crosspoint
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 3. Address Demultiplex/Data Buffering
Figure 4. Data Bus Byte Swapper
Figure 5. Four-Port Memory Interface
Applications (Cont.)
Note: All OE and SEL lines driven by external arbiter logic (not shown).
D8-15
D0-7
I/OA
OEA OEB
I/OA
OEA OEB
XCVR
XCVR
I/OA
OEA OEB
D
CLK
Address
I/OB
I/OB
XCVR
Latch
Port #1
OE1
Port #2
OE2
Port #3
OE3
Port #4
OE4
I/OB
Bidirectional
16-Bit MUX
Q
4-to-1
Memory
I/OA
OEA OEB
I/OA
OEA OEB
D8-15
D0-7
XCVR
SEL0
SEL1
XCVR
OEM
Port
Address
Buffered
Data
I/OB
I/OB
To Memory/
Peripherals
To
Memory
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Specifications ispGDX Family
Designing with the ispGDX
As mentioned earlier, this architecture satisfies the PRSI
class of applications without restrictions: any I/O pin as a
single input or bidirectional can drive any other I/O pin as
output.
For the case of PDP applications, the designer does have
to take into consideration the limitations on pins that can
be used as control (MUX0, MUX1, OE, CLK) or data
(MUXA-D) inputs. The restrictions on control inputs are
not likely to cause any major design issues because the
input possibilities span 25% of the total pins.
The MUXA-D input partitioning requires that designers
consciously assign pinouts so that MUX inputs are in the
appropriate, disjoint groups. For example, since the
MUXA group includes I/O0-19 (80 I/O device), it is not
possible to use I/O0 and I/O9 in the same MUX function.
As previously discussed, data path functions will be
assigned early in the design process and these restric-
tions are reasonable in order to optimize speed and cost.
User Electronic Signature
The ispGDX Family includes dedicated User Electronic
Signature (UES) E
design-specific information into the devices to identify
particular manufacturing dates, code revisions, or the
like. The UES information is accessible through the
boundary scan or Lattice ISP programming port via a
specific command. This information can be read even
when the security cell is programmed.
Security Bit
The ispGDX Family includes a security bit feature that
prevents reading the device program once set. Even
when set, it does not inhibit reading the UES or device ID
code. It can be erased only via a device bulk erase.
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CMOS storage to allow users to code