ISPGDX120A-5Q160 Lattice, ISPGDX120A-5Q160 Datasheet - Page 2

• Manufacturer Part Number: ISPGDX120A-5Q160
• Description: Analog & Digital Crosspoint ICs PROGRAMMABLE GEN DIG CROSSPOINT
• Manufacturer: Lattice

Specifications of ISPGDX120A-5Q160

• Mounting Style: SMD/SMT
• Number Of Arrays: 1
• Operating Supply Voltage: 5 V
• Supply Type: Single
• Configuration: 120 x 120
• Package / Case: TSSOP-24
• Input Level: TTL
• Output Level: TTL
• Supply Voltage (max): 5.25 V
• Supply Voltage (min): 4.75 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Product: Digital Crosspoint
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

• IN-SYSTEM PROGRAMMABLE GENERIC DIGITAL
• HIGH PERFORMANCE E
• ispGDX OFFERS THE FOLLOWING ADVANTAGES
• FLEXIBLE ARCHITECTURE
Copyright © 2002 Lattice Semiconductor Corporation. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein
are subject to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. [phone]; 1-800-LATTICE; FAX [phone]; http://www.latticesemi.com
ispgdx_11
Features
CROSSPOINT FAMILY
— Advanced Architecture Addresses Programmable
— Three Device Options: 80 to 160 Programmable I/O
— “Any Input to Any Output” Routing
— Fixed HIGH or LOW Output Option for Jumper/DIP
— Space-Saving TQFP, PQFP and BGA Packaging
— Dedicated IEEE 1149.1-Compliant Boundary Scan
— PCI Compliant Output Drive
— 5V Power Supply
— 5.0ns Input-to-Output/5.0ns Clock-to-Output Delay
— Low-Power: 40mA Quiescent Icc
— Balanced 24mA Output Buffers with Programmable
— Schmitt Trigger Inputs for Noise Immunity
— Electrically Erasable and Reprogrammable
— Non-Volatile E
— 100% Tested
— In-System Programmable
— Lattice ISP or JTAG Programming Interface
— Only 5V Power Supply Required
— Change Interconnects in Seconds
— Reprogram Soldered Devices
— Combinatorial/Latched/Registered Inputs or Outputs
— Individual I/O Tri-state Control with Polarity Control
— Dedicated Clock Input Pins (two or four) or
— Up to 4:1 Dynamic Path Selection
— Programmable Output Pull-up Resistors
— Outputs Tri-state During Power-up (“Live Insertion”
PCB Interconnect, Bus Interface Integration and
Jumper/Switch Replacement
Pins
Switch Emulation
Test
Slew Rate Control
Programmable Clocks from I/O Pins (from 20 up to
40)
Friendly)
2
CMOS Technology
2
CMOS
®
TECHNOLOGY
1
The ispGDX architecture provides a family of fast, flexible
programmable devices to address a variety of system-
level digital signal routing and interface requirements
including:
The ispGDX Family consists of three members with 80,
120 and 160 Programmable I/Os. These devices are
available in packages ranging from the 100-pin TQFP to
the 208-pin PQFP. The devices feature fast operation,
with input-to-output signal delays (Tpd) of 5ns and clock-
to-output delays of 5ns.
The architecture of the devices consists of a series of
programmable I/O cells interconnected by a Global Rout-
Functional Block Diagram
Description
Boundary
• Multi-Port Multiprocessor Interfaces
• Wide Data and Address Bus Multiplexing
• Programmable Control Signal Routing
• Board-Level PCB Signal Routing for Prototyping or
Control
Scan
(e.g. 4:1 High-Speed Bus MUX)
(e.g. Interrupts, DMAREQs, etc)
Programmable Bus Interfaces
Cells
I/O
ispGDX
Generic Digital Crosspoint
Global Routing
In-System Programmable
I/O Pins D
I/O Pins B
(GRP)
Pool
®
Family
November 2003
Cells
I/O
Control
ISP