DS26528-W Maxim Integrated Products, DS26528-W Datasheet - Page 3

• Manufacturer Part Number: DS26528-W
• Description: Network Controller & Processor ICs Octal E1-T1-J1 Singl e-Chip Transceiver (
• Manufacturer: Maxim Integrated Products

Specifications of DS26528-W

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9.
10.
11.
12.
13.
8.10
8.11
8.12
9.1
9.2
9.3
9.4
9.5
9.6
10.1
10.2
10.3
10.4
11.1
11.2
12.1
12.2
12.3
13.1
8.9.12
8.9.13
8.9.14
8.9.15
8.9.16
8.9.17
8.10.1
8.10.2
8.11.1
8.11.2
8.11.3
8.11.4
8.11.5
8.12.1
8.12.2
9.1.1
9.1.2
9.1.3
9.2.1
9.2.2
9.2.3
9.2.4
9.4.1
9.4.2
13.1.1
13.1.2
13.1.3
13.1.4
DEVICE REGISTERS .......................................................................................................88
FUNCTIONAL TIMING ...................................................................................................235
OPERATING PARAMETERS.........................................................................................250
AC TIMING CHARACTERISTICS ..................................................................................252
JTAG BOUNDARY SCAN AND TEST ACCESS PORT ................................................263
R
R
G
F
LIU R
BERT R
RAMER
EGISTER
EGISTER
LOBAL
HDLC C
L
B
T1 R
T1 T
E1 R
E1 T
T
L
M
JTAG I
S
TAP C
INE
INE
HERMAL
IT
YSTEM
ICROPROCESSOR
Receive Per-Channel Idle Code Insertion............................................................................................ 64
Per-Channel Loopback ........................................................................................................................ 64
E1 G.706 Intermediate CRC-4 Updating (E1 Mode Only) ................................................................... 64
T1 Programmable In-Band Loop Code Generator............................................................................... 65
T1 Programmable In-Band Loop Code Detection................................................................................ 66
Framer Payload Loopbacks ................................................................................................................. 67
Receive HDLC Controller..................................................................................................................... 68
Transmit HDLC Controller.................................................................................................................... 71
LIU Operation....................................................................................................................................... 76
Transmitter ........................................................................................................................................... 77
Receiver ............................................................................................................................................... 80
Jitter Attenuator.................................................................................................................................... 83
LIU Loopbacks ..................................................................................................................................... 84
BERT Repetitive Pattern Set ............................................................................................................... 87
BERT Error Counter............................................................................................................................. 87
Global Register List.............................................................................................................................. 90
Framer Register List............................................................................................................................. 91
LIU and BERT Register List................................................................................................................. 98
Global Register Bit Map ....................................................................................................................... 99
Framer Register Bit Map .................................................................................................................... 100
LIU Register Bit Map .......................................................................................................................... 108
BERT Register Bit Map ...................................................................................................................... 108
Receive Register Definitions.............................................................................................................. 124
Transmit Register Definitions............................................................................................................. 183
Test-Logic-Reset................................................................................................................................ 264
Run-Test-Idle ..................................................................................................................................... 264
Select-DR-Scan ................................................................................................................................. 264
Capture-DR ........................................................................................................................................ 264
-E
EGISTER
RANSMITTER
RANSMITTER
I
ECEIVER
I
ECEIVER
NTERFACE
RROR
NTERFACE
R
EGISTER
R
ONTROLLER
NTERFACE
EGISTER
EGISTER
L
B
ONTROLLERS
C
ISTINGS
C
IT
LOCK
-R
HARACTERISTICS
M
D
ATE
F
APS
F
EFINITIONS
D
UNCTIONAL
UNCTIONAL
AC C
U
C
D
EFINITIONS
D
F
F
T
......................................................................................................................88
......................................................................................................................99
T
NITS
HARACTERISTICS
EFINITIONS
EFINITIONS
S
UNCTIONAL
EST
UNCTIONAL
B
IMING
TATE
US
HARACTERISTICS
................................................................................................................68
(LIU
(BERT) F
AC C
.........................................................................................................218
.........................................................................................................261
M
T
T
S
.....................................................................................................227
ACHINE
IMING
....................................................................................................251
IMING
)....................................................................................................73
..................................................................................................109
HARACTERISTICS
.................................................................................................124
T
T
IMING
IMING
UNCTION
D
D
..........................................................................................251
.........................................................................................264
IAGRAMS
IAGRAMS
D
D
....................................................................................262
3 of 276
IAGRAMS
IAGRAMS
................................................................................86
..........................................................................235
..........................................................................245
........................................................................252
....................................................................240
....................................................................247
DS26528 Octal T1/E1/J1 Transceiver