DS34S101GN Maxim Integrated Products, DS34S101GN Datasheet - Page 9

• Manufacturer Part Number: DS34S101GN
• Description: Communication ICs - Various Single TDM-Over-Pack et Transport Devices
• Manufacturer: Maxim Integrated Products

TDMoP Delay Variation Compensation
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TDMoP CAS Support
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Test and Diagnostics
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CPU Interface
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6 Overview of Major Operational Modes
Globally, the resources of the device can be committed to either one high-speed E3, T3 or STS-1 TDM stream
(high-speed mode) or one or more E1, T1 or serial streams (normal low-speed mode). In high-speed mode, the
TDM signal is carried using an unstructured AAL1 or SAToP mapping. High-speed mode is enabled by setting
General_cfg_reg0.High_speed=1.
In normal, low-speed mode, each port can be configured for E1, T1 or serial (e.g. V.35) operation. Ports configured
for E1 or T1 can be further configured for unframed, framed, or multiframed interface. In addition, each port can be
configured to have the transmit and receive directions clocked by independent clocks (two-clock mode) or to have
both directions clocked by the transmit clock (one-clock mode). All of this configuration is specified in the per-port
Port[n]_cfg_reg register.
Rev: 032609
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
Configurable jitter buffers compensate for delay variation introduce by the IP/MPLS/Ethernet network
Large maximum jitter buffer depths:
Packet reordering is performed for SAToP and CESoPSN bundles within the range of the jitter buffer
Packet loss is compensated by inserting either a pre-configured conditioning value or the last received value.
On-chip CAS handler terminates E1/T1 CAS when using AAL1/CESoPSN in structured-with-CAS mode.
CPU intervention is not required for CAS handling.
IEEE 1149.1 JTAG support
MBIST (memory built-in self test)
32 or 16-bit parallel interface or optional SPI serial interface
Byte write enable pins for single-byte write resolution
Hardware reset pin
Software reset supported
Software access to device ID and silicon revision
On-chip SDRAM controller provides access to SDRAM for both the chip and the CPU
CPU can access transmit and receive buffers in SDRAM used for packets to/from the CPU (ARP, SNMP, etc.)
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Automatic transition to holdover when link break is detected
E1: up to 256 ms
T1 unframed: up to 340 ms
T1 framed: up to 256 ms
T1 framed with CAS: up to 192 ms
E3: up to 60 ms
T3: up to 45 ms
STS-1: up to 40 ms.
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