CY28447LFXC Silicon Laboratories Inc, CY28447LFXC Datasheet - Page 7

• Manufacturer Part Number: CY28447LFXC
• Description: Clock Generators & Support Products Calistoga System Clk Extra SRC Output
• Manufacturer: Silicon Laboratories Inc

Specifications of CY28447LFXC

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Rev 1.0, November 20, 2006
Byte 5: Control Register 5 (continued)
Byte 6: Control Register 6
Byte 7: Vendor ID
Byte 8: Control Register 8
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Bit
Bit
Bit
Bit
1
1
0
7
6
5
4
3
2
0
@Pup
@Pup
@Pup
@Pup
HW
HW
HW
0
0
0
0
1
1
1
0
0
0
0
0
1
1
1
0
0
0
1
1
0
0
0
PCI, PCIF and SRC clock
outputs except those set
Revision Code Bit 3
Revision Code Bit 2
Revision Code Bit 1
Revision Code Bit 0
Vendor ID Bit 3
Vendor ID Bit 2
Vendor ID Bit 1
Vendor ID Bit 0
to free running
TEST_MODE
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
TEST_SEL
CPU[T/C]1
CPU[T/C]0
USB_48M
PCIF0
Name
Name
Name
REF1
REF0
Name
FSC
FSB
FSA
CPU[T/C]1 PWRDWN Drive Mode
CPU[T/C]0 PWRDWN Drive Mode
REF/N or Tri-state Select
0 = Tri-state, 1 = REF/N Clock
Test Clock Mode Entry Control
0 = Normal operation, 1 = REF/N or Tri-state mode,
REF1 Output Drive Strength
0 = Low, 1 = High
REF0 Output Drive Strength
0 = Low, 1 = High
SW PCI_STP Function
0=SW PCI_STP assert, 1= SW PCI_STP deassert
When this bit is set to 0, all STOPPABLE PCI, PCIF and SRC outputs will
be stopped in a synchronous manner with no short pulses.
When this bit is set to 1, all STOPPED PCI, PCIF and SRC outputs will
resume in a synchronous manner with no short pulses.
FSC Reflects the value of the FSC pin sampled on power up
0 = FSC was low during VTT_PWRGD# assertion
FSB Reflects the value of the FSB pin sampled on power up
0 = FSB was low during VTT_PWRGD# assertion
FSA Reflects the value of the FSA pin sampled on power up
0 = FSA was low during VTT_PWRGD# assertion
RESERVED, Set = 0
RESERVED, Set = 0
RESERVED, Set = 0
RESERVED, Set = 0
RESERVED, Set = 0
USB_48MHz Output Drive Strength
0= Low, 1= High
RESERVED, Set = 1
PCIF0 Output Drive Strength
0 = Low, 1 = High
0 = Driven when PD asserted,1 = Tri-state when PD asserted
0 = Driven when PD asserted,1 = Tri-state when PD asserted
Revision Code Bit 3
Revision Code Bit 2
Revision Code Bit 1
Revision Code Bit 0
Vendor ID Bit 3
Vendor ID Bit 2
Vendor ID Bit 1
Vendor ID Bit 0
Description
Description
Description
Description
CY28447
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