CY28447LFXC Silicon Laboratories Inc, CY28447LFXC Datasheet - Page 10

• Manufacturer Part Number: CY28447LFXC
• Description: Clock Generators & Support Products Calistoga System Clk Extra SRC Output
• Manufacturer: Silicon Laboratories Inc

Specifications of CY28447LFXC

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Rev 1.0, November 20, 2006
Calculating Load Capacitors
In addition to the standard external trim capacitors, trace
capacitance and pin capacitance must also be considered to
correctly calculate crystal loading. As mentioned previously,
the capacitance on each side of the crystal is in series with the
crystal. This means the total capacitance on each side of the
crystal must be twice the specified crystal load capacitance
(CL). While the capacitance on each side of the crystal is in
series with the crystal, trim capacitors (Ce1,Ce2) should be
calculated to provide equal capacitive loading on both sides.
As mentioned previously, the capacitance on each side of the
crystal is in series with the crystal. This means the total capac-
itance on each side of the crystal must be twice the specified
load capacitance (CL). While the capacitance on each side of
the crystal is in series with the crystal, trim capacitors
Cs1
Figure 1. Crystal Capacitive Clarification
Figure 2. Crystal Loading Example
Ce1
X1
SRCC(free running)
SRCT(free running)
Ci1
SRCT(stoppable)
SRCT(stoppable)
Clock Chip
CLKREQ#X
XTAL
Ci2
Figure 3. CLK_REQ#[1:9] Deassertion/Assertion Waveform
X2
Ce2
Cs2
3 to 6p
33 pF
Trim
Pin
2.8 pF
Trace
(Ce1,Ce2) should be calculated to provide equal capacitance
loading on both sides.
Use the following formulas to calculate the trim capacitor
values for Ce1 and Ce2.
CL....................................................Crystal load capacitance
CLe......................................... Actual loading seen by crystal
using standard value trim capacitors
Ce..................................................... External trim capacitors
Cs .............................................. Stray capacitance (terraced)
Ci ...........................................................Internal capacitance
(lead frame, bond wires etc.)
CLK_REQ# Description
The CLKREQ# signals are active LOW inputs used for clean
enabling and disabling selected SRC outputs. The outputs
controlled by CLKREQ# are determined by the settings in
register byte 8. The CLKREQ# signal is a de-bounced signal
in that it’s state must remain unchanged during two consec-
utive rising edges of SRCC to be recognized as a valid
assertion or deassertion. (The assertion and deassertion of
this signal is absolutely asynchronous.)
CLK_REQ[1:9]# Assertion (CLKREQ# -> LOW)
All differential outputs that were stopped are to resume normal
operation in a glitch-free manner. The maximum latency from
the assertion to active outputs is between 2 and 6 SRC clock
periods (2 clocks are shown) with all SRC outputs resuming
simultaneously. All stopped SRC outputs must be driven HIGH
within 10 ns of CLKREQ# deassertion to a voltage greater than
200 mV.
CLK_REQ[1:9]# Deassertion (CLKREQ# -> HIGH)
The impact of deasserting the CLKREQ# pins is that all SRC
outputs that are set in the control registers to stoppable via
deassertion of CLKREQ# are to be stopped after their next
transition. The final state of all stopped DIF signals is LOW,
both SRCT clock and SRCC clock outputs will not be driven.
CLe
Total Capacitance (as seen by the crystal)
=
(
Load Capacitance (each side)
Ce1 + Cs1 + Ci1
Ce = 2 * CL – (Cs + Ci)
1
+
1
Ce2 + Cs2 + Ci2
1
CY28447
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