CS4222-KS Cirrus Logic Inc, CS4222-KS Datasheet - Page 16

• Manufacturer Part Number: CS4222-KS
• Description: Audio CODECs IC 20-Bit Stereo Codec w/Vol Cntrl
• Manufacturer: Cirrus Logic Inc

Specifications of CS4222-KS

• Number Of Adc Inputs: 2
• Number Of Dac Outputs: 2
• Conversion Rate: 48 KSPs
• Interface Type: Serial (I2C, SPI)
• Resolution: 20 bit
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: SSOP-28
• Minimum Operating Temperature: - 10 C
• Number Of Channels: 2 ADC, 2 DAC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

De-Emphasis
The CS4222 is capable of digital de-emphasis
for 32, 44.1, or 48 kHz sample rates.
mentation of digital de-emphasis requires
reconfiguration of the digital filter to maintain
the filter response shown in Figure 10 at multi-
ple sample rates.
De-emphasis control is achieved with the
DEM1/0 pins or through the DEM2-0 bits in the
DAC Control Byte (#2). The default state on
power-up is de-emphasis controlled via the
DEM1/0 pins (DEM2-0 bits=0). DEM1/0 pin
control is defined in Table 4.
-10dB
16
Gain
dB
0dB
DEM 1
0
0
1
1
Table 4. De-Emphasis filter control
Figure 10. De-emphasis Curve.
T1=50 s
F1
DEM 0
0
1
0
1
F2
De-emphasis
44.1 kHz
32 kHz
48 kHz
T2 = 15 s
OFF
Frequency
Imple-
Power-up/Reset/Power Down/Calibration
Upon power up, the user should hold RST=0 for
approximately 10 ms. In this state, the control
port is reset to its default settings and the part
remains in the power down mode. At the end of
RST, the device performs an offset calibration
which lasts approximately 50 ms after which the
device enters normal operation. A calibration
may also be initiated via the CAL bit in the
ADC Control Byte (#1). The CALP bit in the
ADC Control Byte is a read only bit indicating
the status of the calibration.
Reset/Power Down is achieved by lowering the
RST pin causing the part to enter power down.
Once RST goes high, the control port is func-
tional and the desired settings should be loaded.
The CS4222 will also enter power down mode if
the master clock source stops for approximately
10 s or if the LRCK is not synchronous to the
master clock. The control port will retain its
current settings.
Additionally, the PDAD (ADC Control Byte #1)
and PDDA (DAC Control Byte #2) bits can be
used to power down the ADC’s and DAC’s inde-
pendently. If both are set to 1, the CS4222 will
power down the entire chip. The control port
will retain its current settings.
The CS4222 will mute the analog outputs and
enter the power down mode if the supply drops
below approximately 4 volts.
Power Supply, Layout and Grounding
The CS4222 should be located on the analog
ground plane along with associated analog cir-
cuitry and should be positioned near the split
between ground planes (see Figure 11). Prefer-
ably, the device should also have its own power
plane. The +5V supply should be connected to
the CS4222 via a ferrite bead, positioned closer
than 1" to the device. A single connection be-
CS4222
DS236PP3