CS4222-KS Cirrus Logic Inc, CS4222-KS Datasheet - Page 15

• Manufacturer Part Number: CS4222-KS
• Description: Audio CODECs IC 20-Bit Stereo Codec w/Vol Cntrl
• Manufacturer: Cirrus Logic Inc

Specifications of CS4222-KS

• Number Of Adc Inputs: 2
• Number Of Dac Outputs: 2
• Conversion Rate: 48 KSPs
• Interface Type: Serial (I2C, SPI)
• Resolution: 20 bit
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: SSOP-28
• Minimum Operating Temperature: - 10 C
• Number Of Channels: 2 ADC, 2 DAC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

not supported in the SPI mode. The next 8 bits
form the Memory Address Pointer (MAP), which
is set to the address of the register that is to be
updated. The next 8 bits are the data which will
be placed into register designated by the MAP.
The CS4222 has a MAP auto increment capabil-
ity, enabled by the INCR bit in the MAP register.
If INCR is a zero, then the MAP will stay con-
stant for successive writes. If INCR is set to a 1,
then MAP will auto increment after each byte is
written, allowing block writes of successive reg-
isters. Register reading from the CS4222 is not
supported in the SPI mode.
I
In I
Data is clocked into and out of the part by the
clock, SCL, with the clock to data relationship as
shown in Figure 9. There is no CS pin. Pin AD0
forms the partial chip address and should be tied
to VD or DGND as desired. The upper 6 bits of
the 7 bit address field must be 001000. To com-
municate with the CS4222 the LSB of the chip
address field, which is the first byte sent to the
CS4222, should match the setting of the AD0
pin. The eighth bit of the address byte is the
R/W bit (high for a read, low for a write). If the
operation is a write, the next byte is the Memory
Address Pointer which selects the register to be
read or written. If the operation is a read, the
contents of the register pointed to by the Mem-
ory Address Pointer will be output. Setting the
auto increment bit in MAP, allows successive
DS236PP3
2
C
2
®
C
Mode
®
mode, SDA is a bidirectional data line.
SDA
SCL
Note: If operation is a write, this byte contains the Memory Address Pointer, MAP.
Start
001000
Figure 9. Control Port Timing, I
ADDR
AD0
R/W
ACK
reads or writes of consecutive registers. Each
byte is separated by an acknowledge bit. Use of
the I
cense from Philips. I
trademark of Philips Semiconductor.
Control Port Bit Definitions
All registers can be written and read in I
mode, except the Converter Status Report Byte
(#6) and the CLKE and CALP bits in the ADC
control byte (#1) which are read only. SPI mode
only allows for register writing. See the follow-
ing bit definition tables for bit assignment
information.
DATA
1-8
2
C bus
Note 1
2
C
ACK
®
Mode
®
compatible interface requires a li-
DATA
1-8
2
ACK
C bus
Stop
®
is a registered
CS4222
2
15
C