CS4205-KQ Cirrus Logic Inc, CS4205-KQ Datasheet - Page 39

• Manufacturer Part Number: CS4205-KQ
• Description: Audio CODECs IC AC'97 Codec for Docking Stations
• Manufacturer: Cirrus Logic Inc

Specifications of CS4205-KQ

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

5.18
ID[1:0]
Default
The Extended Modem ID Register (Index 3Ch) is a read/write register that identifies the CS4205 modem capabilities.
Writing any value to this location issues a reset to modem registers (Index 3Ch-54h), including GPIO registers
(Index 4Ch - 54h). Audio registers are not reset by a write to this location.
5.19
PRA
GPIO
Default
5.20
GC[4:0]
Default
After a Cold Reset or a modem Register Reset (see Extended Modem ID Register (Index 3Ch)), all GPIO pins are
configured as inputs. The upper 11 bits of this register always return ‘0’.
DS489PP4
D15
D15
D15
ID1
0
0
Extended Modem ID Register (Index 3Ch)
Extended Modem Status/Control Register (Index 3Eh)
GPIO Pin Configuration Register (Index 4Ch)
D14
D14
D14
ID0
0
0
D13
D13
D13
0
0
0
CS4205 is the primary audio codec. When ID[1:0] = 01, 10, or 11, the CS4205 is a secondary
audio codec. The state of the ID[1:0] bits is determined at power-up from the ID[1:0]# pins
and the current clocking scheme, see Table 27 on page 63.
GPIO Pin Configuration. When ‘set’, the GC[4:0] bits define the corresponding GPIO pin as
an input. When ‘clear’, the corresponding GPIO pin is defined as an output. When the SDEN
bit in the Serial Port Control Register (Index 6Ah) is ‘set’, the GC[1:0] bits are read-only bits
and always return ‘0’. When SDEN is ‘clear’, the GC[1:0] bits function normally. Likewise,
GC2 depends on SDI1, GC3 depends on SDI2, and GC4 depends on SDI3. The SDI[1:3] bits
are located in the Serial Port Control Register (Index 6Ah).
001Fh. This value corresponds to all GPIO pins configured as inputs.
Codec ID. These bits indicate the current codec configuration. When ID[1:0] = 00, the
x000h. This value indicates no supported modem functions.
GPIO Powerdown. When ‘set’, the PRA bit powers down the GPIO subsystem. When the
GPIO section is powered down, all outputs must be tri-stated and input Slot 12 should be
marked invalid when the AC-link is active. To use any GPIO functionality, including Internal
Error Signaling, PRA must be cleared first.
GPIO. When ‘set’, the GPIO bit indicates the GPIO subsystem is ready for use. When ‘set’,
input Slot 12 will also be marked valid.
0100h
D12
D12
D12
0
0
0
D11
D11
D11
0
0
0
D10
D10
D10
0
0
0
D9
D9
D9
0
0
0
PRA
D8
D8
D8
0
0
D7
D7
D7
0
0
0
D6
D6
D6
0
0
0
D5
D5
D5
0
0
0
GC4
D4
D4
D4
0
0
GC3
D3
D3
D3
0
0
GC2
D2
D2
D2
0
0
CS4205
GC1
D1
D1
D1
0
0
GPIO
GC0
D0
D0
D0
0
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