CS4205-KQ Cirrus Logic Inc, CS4205-KQ Datasheet - Page 10

• Manufacturer Part Number: CS4205-KQ
• Description: Audio CODECs IC AC'97 Codec for Docking Stations
• Manufacturer: Cirrus Logic Inc

Specifications of CS4205-KQ

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AC ’97 SERIAL PORT TIMING
AVdd = 5.0 V, DVdd = 3.3 V; C
10
RESET Timing
RESET# active low pulse width
RESET# inactive to BIT_CLK start-up delay
1st SYNC active to CODEC READY ‘set’
Vdd stable to RESET# inactive
Clocks
BIT_CLK frequency
BIT_CLK period
BIT_CLK output jitter (depends on XTL_IN source)
BIT_CLK high pulse width
BIT_CLK low pulse width
SYNC frequency
SYNC period
SYNC high pulse width
SYNC low pulse width
Data Setup and Hold
Output propagation delay from rising edge of BIT_CLK
Input setup time from falling edge of BIT_CLK
Input hold time from falling edge of BIT_CLK
Input signal rise time
Input signal fall time
Output signal rise time
Output signal fall time
Misc. Timing Parameters
End of Slot 2 to BIT_CLK, SDATA_IN low (PR4)
SYNC pulse width (PR4) Warm Reset
SYNC inactive (PR4) to BIT_CLK start-up delay
Setup to trailing edge of RESET# (ATE test mode) (Note 4) T
Rising edge of RESET# to Hi-Z delay
Parameter
L
= 55 pF load.
Standard test conditions unless otherwise noted: T
(OSC mode)
(XTL mode)
(PLL mode)
(Note 4)
(Note 4)
(Note 4)
T
T
T
T
sync_period
T
T
T
T
Symbol
T
T
T
clk_period
T
sync_high
s2_pdown
T
sync_low
setup2rst
sync2crd
T
sync_pr4
sync2clk
vdd2rst#
clk_high
F
T
T
clk_low
T
rst_low
T
rst2clk
T
F
isetup
T
T
ihold
orise
sync
irise
ofall
ifall
clk
co
off
162.8
Min
100
1.0
1.0
36
36
10
15
8
0
2
2
2
2
-
-
-
-
-
-
-
-
-
-
-
-
-
12.288
62.5
81.4
40.7
40.7
20.8
19.5
Typ
285
4.0
4.0
2.5
1.3
0.2
48
10
4
4
-
-
-
-
-
-
-
-
-
-
ambient
Max
750
1.0
45
45
12
25
-
-
-
6
6
6
6
-
-
-
-
-
-
-
-
-
-
-
-
-
-
CS4205
= 25° C,
DS489PP4
MHz
Unit
kHz
ms
µs
µs
µs
µs
µs
ns
ps
ns
ns
µs
µs
µs
ns
ns
ns
ns
ns
ns
ns
µs
µs
ns
ns
ns