WM8900LGEFK/RV Wolfson Microelectronics, WM8900LGEFK/RV Datasheet - Page 73

• Manufacturer Part Number: WM8900LGEFK/RV
• Description: Audio CODECs Ultra Low Power Hi-Fi CODEC
• Manufacturer: Wolfson Microelectronics

Specifications of WM8900LGEFK/RV

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Production Data
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See “Clocking and Sample Rates” for the definition of how the clock frequencies are set.
Table 52 Master Clock Controls
COMPANDING
The WM8900 supports A-law and µ-law companding on both transmit (ADC) and receive (DAC)
sides. Companding can be enabled on the DAC or ADC audio interfaces by writing the appropriate
value to the DAC_COMP or ADC_COMP register bits respectively.
Table 53 Companding Control
Companding involves using a piecewise linear approximation of the following equations (as set out
by ITU-T G.711 standard) for data compression:
A-law (where A=87.6 for Europe):
The companded data is also inverted as recommended by the G.711 standard (all 8 bits are
inverted for µ-law, all even data bits are inverted for A-law). The data will be transmitted as the
first 8 MSB’s of data.
Companding converts 13 bits (µ-law) or 12 bits (A-law) to 8 bits using non-linear quantization. The
input data range is separated into 8 levels, allowing low amplitude signals better precision than that
of high amplitude signals. This is to exploit the operation of the human auditory system, where
louder sounds do not require as much resolution as quieter sounds. The companded signal is an
8-bit word containing sign (1-bit), exponent (3-bits) and mantissa (4-bits).
R6 (06h)
Clocking 1
R8 (08h)
Audio
Interface 3
R9 (09h)
Audio
Interface 4
R5 (05h)
Audio
Interface 2
REGISTER
ADDRESS
REGISTER
ADDRESS
µ-law (where µ=255 for the U.S. and Japan):
F(x) = ln( 1 + µ|x|) / ln( 1 + µ)
F(x) = A|x| / ( 1 + lnA)
F(x) = ( 1 + lnA|x|) / (1 + lnA)
4
3
2
1
BIT
0
11
11
BIT
DAC_COMP
DAC_COMPMODE
ADC_COMP
ADC_COMPMODE
BCLK_DIR
ADCLRC_DIR
DACLRC_DIR
LABEL
LABEL
-1 ≤ x ≤ 1
0
0
0
DEFAULT
0
0
0
0
DEFAULT
} for x ≤ 1/A
} for 1/A ≤ x ≤ 1
BCLK Direction
0 = BCLK is input
1 = BCLK is output
ADCLRC Direction
0 = ADCLRC is input
1 = ADCLRC is output
DACLRC Direction
0 = DACLRC is input
1 = DACLRC is output
DAC Companding enable
0 = off
1 = on
DAC Companding mode select:
0 = µ-law
1 = A-law
ADC Companding enable
0 = off
1 = on
ADC Companding mode select:
0 = µ-law
1 = A-law
PD, August 2008, Rev 4.0
DESCRIPTION
DESCRIPTION
WM8900
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