CS8427-CSZR Cirrus Logic Inc, CS8427-CSZR Datasheet - Page 15

• Manufacturer Part Number: CS8427-CSZR
• Description: Audio DSPs IC 96 kHz Digital Audio Transceiver
• Manufacturer: Cirrus Logic Inc

Specifications of CS8427-CSZR

• Operating Temperature Range: - 10 C to + 70 C
• Mounting Style: SMD/SMT
• Package / Case: SOIC-28
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

5. THREE-WIRE SERIAL AUDIO PORTS
A 3-wire serial audio input port and a 3-wire serial
audio output port is provided. Each port can be ad-
justed to suit the attached device by setting the
control registers. The following parameters are ad-
justable: master or slave, serial clock frequency,
audio data resolution, left or right justification of the
data relative to left/right clock, optional 1-bit cell
delay of the 1st data bit, the polarity of the bit clock,
and the polarity of the left/right clock. By setting the
appropriate control bits, many formats are possi-
ble.
Figure 15
mats, along with the control bit settings. It should
be noted that in right justified mode, the serial au-
dio output data is “MSB extended”. This means
that in a sub-frame where the MSB of the data is
'1', all bits preceding the MSB in the sub-frame will
also be '1'. Conversely, in a sub-frame where the
MSB of the data is '0', all bits preceding the MSB in
the sub-frame will also be '0'.
The clocking of the input section of the CS8427
may be derived from the incoming ILRCK word
rate clock, using the on-chip PLL. The PLL opera-
tion is described in
the case of use with the serial audio input port, the
PLL locks onto the leading edges of the ILRCK
clock.
DS477F5
shows a selection of common input for-
“AES3 Receiver” on page
16. In
Figure 16
mats, along with the control bit settings. A special
AES3 direct output format is included, which allows
serial output port access to the V, U, and C bits em-
bedded in the serial audio data stream. The P bit is
replaced by a Z bit that marks the subframe just pri-
or to the start of each block. This format is only
available when the serial audio output port is being
clocked by the AES3 receiver recovered clock.
In master mode, the left/right clock and the serial
bit clock are outputs, derived from the appropriate
clock domain master clock.
In slave mode, the left/right clock and the serial bit
clock are inputs. The left/right clock must be syn-
chronous to the appropriate master clock, but the
serial bit clock can function in asynchronous burst
mode if desired. By appropriate phasing of the
left/right clock and control of the serial clocks,
CS8427’s can be multiplexed to share one serial
port. The left/right clock should be continuous, but
the duty cycle does not have to be 50%, provided
that enough serial clocks are present in each
phase to clock all the data bits. When in slave
mode, the serial audio output port must not be set
to right justified data.
When using the serial audio output port in slave
mode with an OLRCK input which is asynchronous
to the port’s data source, an interrupt bit (OSLIP) is
provided to indicate when repeated or dropped
samples occur.
shows a selection of common output for-
CS8427
15