CYII4SM6600AB-QWC Cypress Semiconductor Corp, CYII4SM6600AB-QWC Datasheet - Page 29

• Manufacturer Part Number: CYII4SM6600AB-QWC
• Description: IC SENSOR IMAGE MONO 68-LCC
• Manufacturer: Cypress Semiconductor Corp
• Type: CMOS Imagingr

Specifications of CYII4SM6600AB-QWC

• Pixel Size: 3.5µm x 3.5µm
• Active Pixel Array: 2210H x 3002V
• Frames Per Second: 5
• Voltage - Supply: 2.5V, 3.3V
• Package / Case: 68-LCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant

Table 15. Pin List (continued)
Note on Power On Behavior
At power on, the chip is in an undefined state. It is advised that the power on is accompanied by the assertion of the SYS_CLOCK
and a SYS_RESET pulse that puts all internal registers in their default state (all bits are set to 0). The X-shift registers are in a defined
state after the first X_SYNC, which occurs a few microseconds after the first Y_START and Y_CLOCK pulse. Before this X_SYNC,
the chip may draw more current from the analog power supply V
supplies. The current spike (if there are any) may also be avoided by a slower ramp up of the analog power supply or by disconnecting
the resistor on pin 3 (CMD_COLAMP) at startup.
Document Number: 001-02366 Rev. *G
64
65
66
67
68
Pin
BS_RESET
BS_CLOCK
BS_DIN
BS_BUS
CMD_DEC
Pin Name
Pin Type
Output
Input
Input
Input
Input
-
-
-
-
0.74
Expected Voltage [V]
DDA
. It is therefore favorable to have separate analog and digital
Boundary scan (allows debugging of internal nodes): Reset.
Tie to GND if not used.
Boundary scan (allows debugging of internal nodes): Clock.
Tie to GND if not used.
Boundary scan (allows debugging of internal nodes): In. Tie
to GND if not used.
Boundary scan (allows debugging of internal nodes): Bus.
Leave floating if not used.
Biasing of X and Y decoder. Connect to V
and decouple to GNDD with C = 100 nF.
IBIS4-6600 CYII4SM6600AB
Pin Description
DDD
with R = 50 k
Page 29 of 34
[+] Feedback