CYII4SM6600AB-QWC Cypress Semiconductor Corp, CYII4SM6600AB-QWC Datasheet - Page 19

• Manufacturer Part Number: CYII4SM6600AB-QWC
• Description: IC SENSOR IMAGE MONO 68-LCC
• Manufacturer: Cypress Semiconductor Corp
• Type: CMOS Imagingr

Specifications of CYII4SM6600AB-QWC

• Pixel Size: 3.5µm x 3.5µm
• Active Pixel Array: 2210H x 3002V
• Frames Per Second: 5
• Voltage - Supply: 2.5V, 3.3V
• Package / Case: 68-LCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant

Table 10. List of Internal Registers (continued)
Register Descriptions
SEQUENCER Register
a.
In normal operation (NDR = 0), the sensor operates in double
sampling mode. At the start of each row readout, the signals from
the pixels are sampled, the row is reset, and the signals from the
pixels are sampled again. The values are subtracted in the
output amplifier.
When NDR is set to 1, the sensor operates in nondestructive
readout (NDR) mode (refer
b.
These bits only influence the operation of the sensor in case
NDR (bit 0) is set to 1. There are two modes for nondestructive
readout (mode 1 and 2). Each mode needs two different frame
readouts (setting 1 and 2 for mode 1, setting 3 and 4 for mode
2). a reset/readout sequence (reset_seq) and then one or
several pure readout sequences (called read_seq hereafter).
Table 11
Table 11. Overview of NDR Modes.
Document Number: 001-02366 Rev. *G
12 (1100)
13 (1101)
14 (1110)
15 (1111)
Register
Setting
NDR (Bit 0)
NDR_mode (Bit 1 and 2)
1
2
3
4
gives an overview of the different NDR modes.
10:0
0
1
2
3
4
5
6:8
9
10
Bit
Bits
00
01
10
11
ADC register
STANDBY_1
STANDBY_2
ONE
SWITCH
EXT_CLK
TRISTATE
DELAY_CLK_ADC
GAMMA
BITINVERT
Reserved
Reserved
Reserved
Table
Name
NDR mode
11).
1
1
2
2
Default value <10:0>:"00000000000"
0 = normal operation
1 = ADC in standby
0 = multiplexing of two ADC outputs
1 = disable multiplexing
if ONE = 0: delay of output with one (EXT_CLK = 0) or half (EXT_CLK = 1) clock cycle
if ONE = 1: switch between two ADCs
0 = internal clock (same as clock to X shift register and output amplifier)
1 = external clock
0 = normal operation
1 = outputs in tristate mode
Delay of clock to ADCs and digital multiplexer
0 = linear conversion
1 = 'gamma' law conversion
0 = no inversion of bits
1 = inversion of bits
Sequence
reset
reset
read
read
Mode 1
In this mode, the sensor is readout in the same method as for the
nondestructive readout. However, electronic shutter control is
not possible in this case, that is, the minimal (integration) time
between two readings is equal to the number of lines that has to
be read out (frame read time). The row lines are clocked
simultaneously (left and right clock pulses are equal).
Mode 2
In this mode, it is possible to have a shorter integration time than
the frame read time. Rows are alternatingly read out with the left
and right pointer. These two pointers can point to two different
rows (see INT_TIME register). The integration time between two
readings of the same row is equal to the number of lines that is
set in the INT_TIME register multiplied by 2 plus 1, and is the
minimal one line read time.
In setting 3, the row that is read out by the left pointer is reset and
read out (first Y_CLOCK), and the row that is read out by the right
pointer is read out without being reset (second Y_CLOCK).
In setting 4, both rows are read out without being reset (on the
first Y_CLOCK the row is read out by the left pointer; on the
second Y_CLOCK the row is read out by the right pointer).
For both modes, the signals are read out through the same path
as with destructive readout (double sampling), but the buses that
are carrying the reset signals in destructive readout, are set to
the voltage given by DAC_DARK in nondestructive readout.
Description
IBIS4-6600 CYII4SM6600AB
Page 19 of 34
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