CYII4SM1300AA-QDC Cypress Semiconductor Corp, CYII4SM1300AA-QDC Datasheet - Page 8

• Manufacturer Part Number: CYII4SM1300AA-QDC
• Description: SENSOR IMAGE MONO CMOS 84-LCC
• Manufacturer: Cypress Semiconductor Corp
• Type: CMOS Imagingr

Specifications of CYII4SM1300AA-QDC

• Package / Case: 84-LCC
• Pixel Size: 7µm² x 7µm²
• Active Pixel Array: 1286H x 1030V
• Frames Per Second: 7
• Voltage - Supply: 5V
• Operating Supply Voltage: 5 V
• Image Size: 1280 H x 1024 V
• Color Sensing: Black/White
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
• Other names: IBIS4-1300-M-2; IBIS4-1300-M-2

Figure 5.
mode. This curve is the relation between the electrons detected
in the pixel and the output signal. This curve was measured with
light of 600 nm, with an integration time of 138.75 ms (10 MHz
pixel rate), at minimal gain setting 0000. The resulting
voltage/electron curve is independent of these parameters. The
conversion gain is 18 µV/electron for this gain setting.
Note that the upper part of the curve (near saturation) is actually
a logarithmic response, similar to the FUGA1000 sensor.
Table 2. Pins of the Image Sensor Core
Document Number: 38-05707 Rev. *C
Digital Controls
SYNC_YR\
CLK_YR
EOS_YR\
SYNC_X\
CLK_X
EOS_X\
SYNC_YL\
CLK_YL
EOS_YL\
SHY
SIN
SELECT
RESET
L/R\
SUBSMPL
Reference Voltages
DCCON
DCREF
NBIASARRAY
PBIAS2
PBIAS
XMUX_NBIAS
GND_AB
shows the pixel response curve in linear response
5
6
7
28
29
8
36
37
38
30
35
40
41
80
84
31
32
1
2
3
4
54
Reset right Y shift register (low active, 0 = sync)
Clock right Y shift register (shifts on falling edge)
(output) low 1st CLK_YR pulse after last row (low active)
Reset X shift register (low active, 0 = sync)
Clock X shift register (shifts on falling edge)
(output) Low 1st CLK_X pulse after last active column (low active)
Reset left Y shift register (low active, 0 = sync)
Clock left Y shift register (shifts on falling edge)
Low 1st CLK_YL pulse after last row
Parallel Y track & hold (1 = hold, 0 = track) apply pulse pattern - see sensor timing diagram
Column amplifier calibration pulse
1 = calibrate - see sensor timing diagram
Selects row indicated by left/right shift register high active (1= select row)
Apply 5 V DC for normal operation
Resets row indicated by left/right shift register high active (1 = reset)
Apply pulse pattern - see timing diagram
Use left or right register for SELECT and RESET
1 = left / 0 = right - see sensor timing
Activate viewfinder mode (1:4 sub sampling = 320 x 256 pixels) high active, 1 = sub
sampling
Control voltage for the DCREF voltage generation Connect to ground by default
Reference voltage (output), to be decoupled to GND
Should be about 1.2V, can be adjusted by DCCON
1 MegaOhm to VDD and decouple to ground by 100 nF capacitor
1 MegaOhm to ground and decouple to VDD by 100 nF capacitor
1 MegaOhm to ground and decouple to VDD by 100 nF capacitor
100K to VDD and decouple to ground by 100 nF capacitor
Anti-blooming drain control voltage
■
■
Default: connect to ground. The anti blooming is operational but not maximal.
Apply about 1 V DC for improved anti-blooming
The level of saturation can be adjusted by the voltage on
GND-AB. However, note also that this logarithmic part of the
response is not FPN corrected by the on-chip offset correction
circuitry.
The signal swing (and thus the dynamic range) is extended by
increasing the Vdd_reset (pins 59/79) To 5.5V. This is mode of
operation is not further documented.
Table 2.
sensor core, describing their functionality.
shows the pins of the IC that are related to the image
CYII4SM1300AA
Page 8 of 35
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