CYII4SM1300AA-QDC Cypress Semiconductor Corp, CYII4SM1300AA-QDC Datasheet - Page 20

• Manufacturer Part Number: CYII4SM1300AA-QDC
• Description: SENSOR IMAGE MONO CMOS 84-LCC
• Manufacturer: Cypress Semiconductor Corp
• Type: CMOS Imagingr

Specifications of CYII4SM1300AA-QDC

• Package / Case: 84-LCC
• Pixel Size: 7µm² x 7µm²
• Active Pixel Array: 1286H x 1030V
• Frames Per Second: 7
• Voltage - Supply: 5V
• Operating Supply Voltage: 5 V
• Image Size: 1280 H x 1024 V
• Color Sensing: Black/White
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
• Other names: IBIS4-1300-M-2; IBIS4-1300-M-2

Set Configuration
Configuration of the image sensor implies control and
adjustment of the following points:
■
■
Viewfinder Mode Versus Normal Readout
Table 8. Coordinate of Row or Column Selected by Y/X Shift Registers After a # Clock Periods in Viewfinder Mode and Full
Image Mode
In full image readout mode (pin 84, subsmpl = 0), the imager is
a 1280 x 1024 SXGA image sensor. There are 3 dummy pixels
read at all 4 borders of the image.
In viewfinder mode (subsmpl = 1), the imager acts as a 320 x 256
QVGA image sensor with one dummy pixel at the start of a
row/column.
Table 8.
of clock pulses.
Document Number: 38-05707 Rev. *C
output amplifier offset level, set by 'dac_bit[0...3]'
output amplifier gain setting, set by 'gc_bit[0...3]'
Viewfinder Mode
Full Image Mode
Viewfinder Mode
Full Image Mode
Clock
Clock
Clock
shows which column or row is selected after a number
Row 1025
Row 1029
Sync
None
None
1030
258
Y Shift Register
Row 1029
Row 1030
None
None
1031
259
1
Row 1
Row 1
Dark
Dark
1032
EOS
EOS
260
2
Row 5
Row 2
Col. 1
Col. 1
■
■
■
Start of the Y Shift Registers for Row Readout and Row Reset
The shift registers are put in their initial state by a
synchronization- or start pulse. (sync_x, sync_yr, sync_yl). The
synchronization signal is low-active and should only be
generated when the clock of the shift register is high. After the
synchronization pulse, two falling clock edges are needed to skip
dummy pixels/lines. On every falling clock edge, the shift register
selects a new row for readout or reset.
timing.
choose the integration time of the next frame
set/clear viewfinder mode (pin 'subsampl')
in case when the fast adjustment of the offset level is used,
plus 'calib_f' and 'unitygain' as described before in
and
3
Figure 8.
Row 9
Row 3
Col. 5
Col. 2
4
Col. 1281
Col. 1285
Row 13
Row 4
Col. 9
Col. 3
1287
322
5
X Shift Register
CYII4SM1300AA
Col. 1285
Col. 1286
Row 17
Col. 13
Row 5
Col. 4
1288
Figure 16.
323
6
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EOS Dark
EOS Dark
shows this
Figure 7.
Y reg.
X reg.
Y reg.
X reg.
1289
324
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