CY7C1380D-250AXC Cypress Semiconductor Corp, CY7C1380D-250AXC Datasheet - Page 7

• Manufacturer Part Number: CY7C1380D-250AXC
• Description: SRAM (Static RAM)
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1380D-250AXC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Memory Size: 18M (512K x 36)
• Speed: 250MHz
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 100-LQFP
• Density: 18Mb
• Access Time (max): 2.6ns
• Sync/async: Synchronous
• Architecture: SDR
• Clock Freq (max): 250MHz
• Operating Supply Voltage (typ): 3.3V
• Address Bus: 19b
• Package Type: TQFP
• Operating Temp Range: 0C to 70C
• Number Of Ports: 4
• Supply Current: 350mA
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Word Size: 36b
• Number Of Words: 512K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 1. Pin Definitions (continued)
Document #: 38-05543 Rev. *F
MODE
TDO
TDI
TMS
TCK
NC
Synchronous
Synchronous
Synchronous
JTAG serial
JTAG serial
Input-Static
JTAG serial
JTAG-
output
Clock
input
input
–
Selects burst order. When tied to GND selects linear burst sequence. When tied to V
floating selects interleaved burst sequence. This is a strap pin and must remain static during
device operation. Mode pin has an internal pull up.
Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the JTAG
feature is not being utilized, this pin must be disconnected. This pin is not available on TQFP
packages.
Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature is
not being utilized, this pin can be disconnected or connected to V
TQFP packages.
Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature is
not being utilized, this pin can be disconnected or connected to V
TQFP packages.
Clock input to the JTAG circuitry. If the JTAG feature is not being utilized, this pin must be
connected to V
No Connects. 36M, 72M, 144M, 288M, 576M, and 1G are address expansion pins and are not
internally connected to the die.
SS
. This pin is not available on TQFP packages.
CY7C1380D, CY7C1382D
CY7C1380F, CY7C1382F
DD
DD
. This pin is not available on
. This pin is not available on
DD
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