CY7C1380D-250AXC Cypress Semiconductor Corp, CY7C1380D-250AXC Datasheet - Page 23

• Manufacturer Part Number: CY7C1380D-250AXC
• Description: SRAM (Static RAM)
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1380D-250AXC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Memory Size: 18M (512K x 36)
• Speed: 250MHz
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 100-LQFP
• Density: 18Mb
• Access Time (max): 2.6ns
• Sync/async: Synchronous
• Architecture: SDR
• Clock Freq (max): 250MHz
• Operating Supply Voltage (typ): 3.3V
• Address Bus: 19b
• Package Type: TQFP
• Operating Temp Range: 0C to 70C
• Number Of Ports: 4
• Supply Current: 350mA
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Word Size: 36b
• Number Of Words: 512K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Switching Waveforms
Document #: 38-05543 Rev. *F
Note
26. On this diagram, when CE is LOW: CE
Data Out (Q)
GW, BWE,
ADDRESS
ADSC
ADSP
BWx
ADV
CLK
OE
CE
t
ADS
t AS
t CES
A1
t
ADH
t AH
t CEH
t
CH
High-Z
t CYC
t WES
t
CL
Single READ
t CLZ
t WEH
t CO
1
is LOW, CE
t ADS
A2
Q(A1)
t ADH
t OEHZ
2
t ADVS
Figure 10. Read Cycle Timing
is HIGH and CE
t ADVH
t OELZ
t OEV
Q(A2)
DON’T CARE
t DOH
t CO
3
is LOW. When CE is HIGH: CE
Q(A2 + 1)
ADV
suspends
burst.
UNDEFINED
Q(A2 + 2)
[26]
BURST READ
1
is HIGH or CE
CY7C1380D, CY7C1382D
Q(A2 + 3)
CY7C1380F, CY7C1382F
2
is LOW or CE
A3
Q(A2)
Burst continued with
new base address
Burst wraps around
to its initial state
Q(A2 + 1)
3
t CHZ
Deselect
cycle
is HIGH.
Page 23 of 34
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