CY7C1347G-166AXIT Cypress Semiconductor Corp, CY7C1347G-166AXIT Datasheet - Page 6

• Manufacturer Part Number: CY7C1347G-166AXIT
• Description: CY7C1347G-166AXIT
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1347G-166AXIT

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Memory Size: 4.5M (128K x 36)
• Speed: 166MHz
• Interface: Parallel
• Voltage - Supply: 3.15 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Pin Definitions
Document #: 38-05516 Rev. *I
A
BW
BW
GW
BWE
CLK
CE
CE
CE
OE
ADV
ADSP
ADSC
ZZ
DQ
DQ
DQP
DQP
V
V
V
V
MODE
0
DD
SS
DDQ
SSQ
,A
1
2
3
A
C
A
C
Name
, DQ
1
, BW
, DQ
A
C
, BW
,A
, DQP
, DQP
B
D
B
D
,
,
,
B
D
,
I/O Power Supply Power Supply for the I/O circuitry.
Asynchronous
Asynchronous
Power Supply
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Input-Clock
I/O Ground
Ground
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Static
I/O-
I/O
Address Inputs Used to Select One of the 128 K Address Locations. Sampled at the rising
edge of the CLK if ADSP or ADSC is active LOW, and CE
A
Byte Write Select Inputs, Active LOW. Qualified with BWE to conduct byte writes to the SRAM.
Sampled on the rising edge of CLK.
Global Write Enable Input, Active LOW. When asserted LOW on the rising edge of CLK, a
global write is conducted (ALL bytes are written, regardless of the values on BW
Byte Write Enable Input, Active LOW. Sampled on the rising edge of CLK. This signal must be
asserted LOW to conduct a byte write.
Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the
burst counter when ADV is asserted LOW, during a burst operation.
Chip Enable 1 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE
only when a new external address is loaded.
Chip Enable 2 Input, Active HIGH. Sampled on the rising edge of CLK. Used in conjunction with
CE
is loaded.
Chip Enable 3 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE
is loaded.
Output Enable, Asynchronous Input, Active LOW. Controls the direction of the I/O pins. When
LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tristated, and act as
input data pins. OE is masked during the first clock of a read cycle when emerging from a
deselected state.
Advance Input Signal, Sampled on the Rising Edge of CLK. When asserted, it automatically
increments the address in a burst cycle.
Address Strobe from Processor, Sampled on the Rising Edge of CLK. When asserted LOW,
addresses presented to the device are captured in the address registers. A
into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP
is ignored when CE
Address Strobe from Controller, Sampled on the Rising Edge of CLK. When asserted LOW,
addresses presented to the device are captured in the address registers. A
into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized.
ZZ “Sleep” Input. This active HIGH input places the device in a non-time-critical “sleep” condition
with data integrity preserved. During normal operation, this pin must be LOW or left floating. ZZ
pin has an internal pull-down.
Bidirectional Data I/O Lines. As inputs, they feed into an on-chip data register that is triggered
by the rising edge of CLK. As outputs, they deliver the data contained in the memory location
specified by the addresses presented during the previous clock rise of the read cycle. The
direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs.
When HIGH, DQs and DQPs are placed in a tristate condition.
Power Supply Inputs to the Core of the Device.
Ground for the Core of the Device.
Ground for the I/O circuitry.
Selects Burst Order. When tied to GND selects linear burst sequence. When tied to V
floating selects interleaved burst sequence. This is a strap pin and must remain static during
device operation. Mode pin has an internal pull-up.
[1:0]
2
1
1
and CE
and CE
and CE
feeds the 2-bit counter.
2
3
3
to select or deselect the device. CE
to select or deselect the device. CE
to select or deselect the device. ADSP is ignored if CE
1
is deasserted HIGH.
Description
2
3
is sampled only when a new external address
is sampled only when a new external address
1
, CE
2
, and CE
1
is HIGH. CE
3
are sampled active.
[1:0]
[1:0]
CY7C1347G
are also loaded
are also loaded
[A:D]
1
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and BWE).
is sampled
DDQ
or left
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