CY7C09569V-100BBC Cypress Semiconductor Corp, CY7C09569V-100BBC Datasheet - Page 10
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CY7C09569V-100BBC
Manufacturer Part Number
CY7C09569V-100BBC
Description
IC,SYNC SRAM,16KX36,CMOS,BGA,172PIN,PLASTIC
Manufacturer
Cypress Semiconductor Corp
Datasheet
1.CY7C09579V-100AXC.pdf
(32 pages)
Specifications of CY7C09569V-100BBC
Format - Memory
RAM
Memory Type
SRAM - Dual Port, Synchronous
Memory Size
576K (16K x 36)
Speed
100MHz
Interface
Parallel
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Package / Case
172-LFBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CY7C09569V-100BBC
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Switching Waveforms
Read Cycle for Flow-Through Output (FT/PIPE = V
Read Cycle for Pipelined Operation (FT/PIPE = V
Notes
Document Number: 38-06054 Rev. *E
12. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge.
13. ADS = V
14. The output is disabled (high-impedance state) by CE=V
15. Addresses do not have to be accessed sequentially since ADS = V
Data
Address
Data
Address
B
CLK
R/W
CLK
R/W
OUT
B
OUT
CE
0-3
OE
IL
OE
CE
0-3
, CNTEN = V
t
t
t
t
t
t
SC
SW
SA
SC
SW
SA
IL
and CNTRST = V
A
A
n
n
t
t
t
t
t
t
t
HC
HW
HA
t
CH2
HC
HW
HA
CH1
t
1 Latency
CKLZ
t
CD1
t
IH
t
CYC2
CYC1
.
t
t
CKLZ
SB
t
t
t
SB
CL2
CL1
IH
A
A
n+1
following the next rising edge of the clock.
n+1
t
Q
DC
t
HB
n
t
t
CD2
IL
HB
constantly loads the address on the rising edge of the CLK. Numbers are for reference only.
IH
IL
)
[12, 13, 14, 15]
)
[12, 13, 14, 15]
Q
A
A
n
n+2
n+2
Q
t
OHZ
n+1
t
DC
Q
t
t
t
SC
OE
SC
t
n+1
t
OLZ
OHZ
A
A
n+3
n+3
t
OLZ
Q
t
DC
n+2
t
t
HC
HC
t
CKHZ
t
OE
CY7C09569V
CY7C09579V
Q
Page 10 of 32
n+2
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