CY7C056V-15AXC Cypress Semiconductor Corp, CY7C056V-15AXC Datasheet - Page 20

• Manufacturer Part Number: CY7C056V-15AXC
• Description: CY7C056V-15AXC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C056V-15AXC

• Format - Memory: RAM
• Memory Type: SRAM - Dual Port, Asynchronous
• Memory Size: 576K (16K x 36)
• Speed: 15ns
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Right Port Configuration
Right Port Operation
Left Port Operation
When reading a semaphore, data lines 0 through 8 output the
semaphore value. The read value is latched in an output register
to prevent the semaphore from changing state during a write
from the other port. If both ports attempt to access the
semaphore within t
obtained by one side or the other, but there is no guarantee which
side will control the semaphore.
When reading a semaphore, data lines 0 through 8 output the
semaphore value. The read value is latched in an output register
to prevent the semaphore from changing state during a write
from the other port. If both ports attempt to access the
semaphore within t
obtained by one side or the other, but there is no guarantee which
side will control the semaphore.
When reading a semaphore, data lines 0 through 8 output the
semaphore value. The read value is latched in an output register
to prevent the semaphore from changing state during a write
from the other port. If both ports attempt to access the
semaphore within t
obtained by one side or the other, but there is no guarantee which
side will control the semaphore.
Document #: 38-06055 Rev. *E
Notes
51. BM and SIZE must be configured one clock cycle before operation is guaranteed.
52. In x36 mode WA and BA pins are “Don’t Care.”
53. In x18 mode BA pin is a “Don’t Care.”
54. DQ represents data output of the chip.
Configuration
BM
x36
x18
x18
x9
x9
x9
x9
0
0
1
1
SPS
SPS
SPS
of each other, the semaphore will definitely be
of each other, the semaphore will definitely be
of each other, the semaphore will definitely be
Control Pin
B0
B1
B2
B3
[51, 52, 53]
WA
X
0
1
0
0
1
1
SIZE
0
1
0
1
BA
X
X
X
0
1
0
1
Bus Match Operation
The right port of the CY7C057V 32Kx36 dual-port SRAM can be
configured in a 36-bit long-word, 18-bit word, or 9-bit byte format
for data I/O. The data lines are divided into four lanes, each
consisting of 9 bits (byte-size data lines).
The bus match select (BM) pin works with bus size select (SIZE)
to select bus width (long-word, word, or byte) for the right port of
the dual-port device. The data sequencing arrangement is
selected using the word address (WA) and byte address (BA)
input pins. A logic “0” applied to both the bus match select (BM)
x36 (CE active SEM mode)
Data Accessed
x36
Configuration
x36 (standard)
/
DQ
DQ
DQ
DQ
DQ
DQ
DQ
x18
16K/32Kx36
CY7C056V
CY7C057V
x9
Dual Port
18–35
18–26
27–35
0–35
0–17
9–17
0–8
I/O
I/O
I/O
I/O
[54]
18–26
27–35
9–17
0–8
Effect
Byte control
Byte control
Byte control
Byte control
9
/
9
/
9
/
9
/
BA WA
BM SIZE
I/O Pins Used
I/O Pins Used
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
CY7C056V
CY7C057V
0–35
0–35
0–17
0–8
0–35
0–17
0–17
x9, x18, x36
0–8
0–8
0–8
0–8
Page 20 of 26
/
[+] Feedback