CS5376A-IQZ Cirrus Logic Inc, CS5376A-IQZ Datasheet - Page 39

• Manufacturer Part Number: CS5376A-IQZ
• Description: IC,Digital Filter,QFP,64PIN,PLASTIC
• Manufacturer: Cirrus Logic Inc

Specifications of CS5376A-IQZ

• Filter Type: Digital
• Number Of Filters: 4
• Max-order: 2nd
• Voltage - Supply: 3 V ~ 5 V
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Package: 64TQFP
• Operating Temperature: -40 to 85 °C
• Resolution (bits): 24bit
• Conversion Rate: 4kSPS
• Operating Temperature Range: -40°C To +85°C
• No. Of Pins: 64
• Msl: MSL 3 - 168 Hours
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1778 - EVALUATION BOARD FOR CS5376
• Frequency - Cutoff Or Center: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10.MODULATOR INTERFACE
The CS5376A performs digital filtering for up to
four ∆Σ modulators. Signals from the modulators
are connected through the modulator data interface
(MDI).
10.1 Pin Descriptions
MCLK, MCLK/2 - Pins 13, 12
Modulator clock outputs. Nominally 2.048 MHz
and 1.024 MHz.
MSYNC - Pin 14
Modulator synchronization signal output. Generat-
ed from the SYNC input.
MDATA1 - MDATA4 - Pins 15, 17, 19, 21
Modulator data inputs, nominally 512 kbit/s.
MFLAG1 - MFLAG4 - Pins 16, 18, 20, 22
Modulator flag inputs. Driven high when modula-
tor is unstable due to an analog over-range signal.
DS612F4
MCLK
MCLK/2
MSYNC
MDATA[4:1]
MFLAG[4:1]
Correction
DC Offset
& Gain
MDI Input
MCLK /
MSYNC
Generate
512 kHz
Figure 20. Modulator Data Interface
CLK
SYNC
Output to High Speed Serial Data Port (SD Port)
SINC
Filter
Output Rate 4000 SPS ~ 1 SPS
10.2 Modulator Clock Generation
The MCLK and MCLK/2 outputs are low-jitter,
low-skew modulator clocks generated from the
32.768 MHz master clock.
MCLK typically operates at 2.048 MHz unless an-
alog low-power modes require a 1.024 MHz mod-
ulator clock. MCLK/2 always produces a clock at
half the selected MCLK rate.
The MCLK rate is selected and the MCLK and
MCLK/2 outputs are enabled by bits in the digital
filter CONFIG register (0x00). By default MCLK
and MCLK/2 are disabled and driven low.
10.3 Modulator Synchronization
The MSYNC output signal follows an input on the
SYNC pin. MSYNC phase aligns the modulator
sampling instant to guarantee synchronous analog
sampling across a measurement network.
MSYNC is enabled by a bit in the CONFIG register
(0x00). By default SYNC inputs do not cause an
MSYNC output.
FIR
Filters
IIR
Filter
CS5376A
39