CS2300P-DZZR Cirrus Logic Inc, CS2300P-DZZR Datasheet - Page 19

• Manufacturer Part Number: CS2300P-DZZR
• Description: IC General Purpose PLL LCO
• Manufacturer: Cirrus Logic Inc
• Type: Fanout Distribution, Fractional N Synthesizerr

Specifications of CS2300P-DZZR

• Pll: Yes
• Input: Clock
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 1:2
• Differential - Input:output: No/No
• Frequency - Max: 75MHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 3.1 V ~ 3.5 V
• Operating Temperature: -10°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 10-MSOP, Micro10™, 10-uMAX, 10-uSOP
• Frequency-max: 75MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1494 - BOARD EVAL GEN PURPOSE PLL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DS844PP2
5.8
5.8.1
5.8.2
5.9
Clock Output Stability Considerations
Required Power Up Sequencing for Programmed Devices
•
•
•
Output Switching
The CS2300-OTP is designed such that re-configuration of the clock routing functions do not result in a
partial clock period on any of the active outputs (CLK_OUT and/or AUX_OUT). In particular, enabling or
disabling an output, and the automatic disabling of the output(s) during unlock will not cause a runt or par-
tial clock period.
The following exceptions/limitations exist:
• Enabling/disabling AUX_OUT when AuxOutSrc = 11 (unlock indicator).
• Switching AuxOutSrc[1:0] to or from 01 (CLK_IN) and to or from 11 (unlock indicator)
When any of these exceptions occur, a partial clock period on the output may result.
PLL Unlock Conditions
Certain changes to the clock inputs and mode pins can cause the PLL to lose lock which will affect the
presence of a clock signal on CLK_OUT. The following outlines which conditions cause the PLL to go un-
locked:
• Any change in the state of the M1 and M0 pins will cause the PLL to temporarily lose lock as the new
• Changes made to the state of the M2 when the M2Config[2:0] global parameter is set to 011, 100, 101,
• Discontinuities on the Frequency Reference Clock, CLK_IN, except when the Clock Skipping feature
• Gradual changes in CLK_IN frequency greater than ±30% from the starting frequency.
• Step changes in CLK_IN frequency.
ification in the
figured by the M0-M2 pins.
Apply power. All input pins should be held in a static logic hi or lo state until the
Apply input clock.
After the specified PLL lock time on
(Transitions between AuxOutSrc[1:0] = [00,10] will not produce a glitch).
setting takes affect.
or 110 can cause the PLL to temporarily lose lock as the new setting takes affect.
is enabled and the requirements of Clock Skipping are satisfied (see
page
10).
“Recommended Operating Conditions” table on page 6
Confidential Draft
page 7
3/18/09
has passed, the device will output the desired clock as con-
are met.
“CLK_IN Skipping Mode” on
‘DC Power
CS2300-OTP
Supply’ spec-
19