CS2300P-DZZR Cirrus Logic Inc, CS2300P-DZZR Datasheet - Page 14

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CS2300P-DZZR

Manufacturer Part Number
CS2300P-DZZR
Description
IC General Purpose PLL LCO
Manufacturer
Cirrus Logic Inc
Type
Fanout Distribution, Fractional N Synthesizerr
Datasheets

Specifications of CS2300P-DZZR

Pll
Yes
Input
Clock
Output
Clock
Number Of Circuits
1
Ratio - Input:output
1:2
Differential - Input:output
No/No
Frequency - Max
75MHz
Divider/multiplier
Yes/Yes
Voltage - Supply
3.1 V ~ 3.5 V
Operating Temperature
-10°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
10-MSOP, Micro10™, 10-uMAX, 10-uSOP
Frequency-max
75MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
598-1494 - BOARD EVAL GEN PURPOSE PLL
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
14
5.4.2
5.4.3
Manual Ratio Modifier (R-Mod)
The manual Ratio Modifier is used to internally multiply/divide the currently addressed R
stored in the register space remain unchanged). The available options for R-Mod are summarized in
Table 2 on page
M2Config[2:0] global parameter (see
Automatic Ratio Modifier (Auto R-Mod)
The Automatic R-Modifier uses the CLK_IN Frequency Range Detector to implement a frequency depen-
dent multiply of the currently addressed R
tor determines the ratio between the frequency of the internal SysClk and the CLK_IN input signal. The
result of the ratio measurement is the internal status signal called FsDetect[1:0].
Like with R-Mod, the Ratio
changed. The Automatic Ratio Modifier is enabled either by the AutoRMod modal parameter or via the
M2 pin in conjunction with the appropriate setting of the M2Config[2:0] global parameter (see
5.7.2 on page
It is important to note that Auto R-Mod (if enabled) is applied in addition to any R-Mod already selected
by the RModSel[1:0] modal parameter and is used to calculate the Effective Ratio (see
page
Auto R-Mod can be used to generate the appropriate oversampling clock (MCLK) for audio A/D and D/A
converters. For example, if the clock applied to CLK_IN is the audio sample rate, Fs (also known as the
word, frame or Left/Right clock), SysClk is the internal LCO (between 13.23 MHz and 16.17 MHz), FsDe-
Referenced Control
Ratio
RModSel[1:0]
M2Config[2:0]........................“M2 Pin Configuration (M2Config[2:0])” on page 22
0-3................................“Ratio 0 - 3” on page 21
15).
........................“R-Mod Selection (RModSel[1:0])” section on page 20
18).
14. R-Mod is enabled via the M2 pin in conjunction with the appropriate setting of the
FsDetect[1:0]
Parameter Definition
00
01
10
RModSel[1:0]
0-3
Table 3. Automatic Ratio Modifier
00
01
10
11
parameters stored in the one time programmable memory remain un-
Table 2. Ratio Modifier
Confidential Draft
Section 5.7.2 on page
f
SysClk
UD
3/18/09
as shown in
96 - 224
> 224
< 96
/ f
CLK_IN
R Modifier
Table
0.0625
0.125
0.25
18).
0.5
Auto R Modifier
3. The CLK_IN Frequency Range Detec-
0.25
0.5
1
CS2300-OTP
Section 5.4.4 on
UD
DS844PP2
(Ratio
Section
0-3

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