CRD42L51 Cirrus Logic Inc, CRD42L51 Datasheet - Page 40

• Manufacturer Part Number: CRD42L51
• Description: Ref Bd Low-voltage Stereo Codec
• Manufacturer: Cirrus Logic Inc

40
4.5.3
4.5.4
4.6
LRCK
SCLK
SDIN
Digital Interface Formats
The serial port operates in standard I²S, Left-Justified or Right-Justified (DAC only) digital interface formats
with varying bit depths from 16 to 24. Data is clocked out of the ADC or into the DAC on the rising edge of
SCLK.
rial Port” on page 20
Hardware
High-Impedance Digital Output
The serial port may be placed on a clock/data bus that allows multiple masters for the serial port I/O with-
out the need for external buffers. The 3ST_SP bit places the internal buffers for these I/O in a high-imped-
ance state, allowing another device to transmit serial port data without bus contention.
Quarter- and Half-Speed Mode
Quarter-Speed Mode (QSM) and Half-Speed Mode (HSM) allow lower sample rates while maintaining a
relatively flat noise floor in the typical audio band of 20 Hz - 20 kHz. Single-Speed Mode (SSM) will allow
lower frequency sample rates; however, the DAC's noise floor, that normally rises out-of-band, will scale
with the lower sample rate and begin to rise within the audio band. QSM and HSM corrects for most of
this scaling, effectively increasing the dynamic range of the CODEC at lower sample rates, relative to
SSM.
Software
Control:
Control:
M S B
Figures 19-21
Transmitting Device #1
“Interface Control (Address 04h)” on page
AOUTA / AINxA
“I²S/LJ” pin 3
L eft C h a n n e l
for exact timing relationship between clocks and data.
Pin
CS42L51
illustrate the general structure of each format. Refer to
3ST_SP
Figure 18. Tri-State Serial Port
Setting
Figure 19. I²S Format
L S B
LO
Receiving Device
HI
SCLK/LRCK
SDOUT
Left-Justified Interface
I²S Interface
52.
M S B
Transmitting Device #2
AOUTB / AINxB
R ig ht C h a n n el
Selection
“Switching Specifications - Se-
L S B
CS42L51
DS679F1
MSB