ADXL345BCCZ-RL Analog Devices Inc, ADXL345BCCZ-RL Datasheet - Page 18

• Manufacturer Part Number: ADXL345BCCZ-RL
• Description: Digital Output Three-Axis Accel 4K RL
• Manufacturer: Analog Devices Inc
• Series: iMEMS®r

Specifications of ADXL345BCCZ-RL

• Design Resources: Sensing Low-g Acceleration Using ADXL345 Digital Accelerometer Connected to ADuC7024 (CN0133)
• Axis: X, Y, Z
• Acceleration Range: ±2g, 4g, 8g, 16g
• Sensitivity: 256LSB/g, 128LSB/g, 64LSB/g, 32LSB/g
• Voltage - Supply: 2 V ~ 3.6 V
• Output Type: Digital
• Bandwidth: 6.25Hz ~ 3.2kHz Selectable
• Interface: I²C, SPI
• Mounting Type: Surface Mount
• Package / Case: 14-LGA
• Package Type: LGA
• Operating Supply Voltage (typ): 2.5V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Product Depth (mm): 3mm
• Product Length (mm): 5mm
• Mounting: Surface Mount
• Pin Count: 14
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ADXL345BCCZ-RLTR

ADXL345
I
With CS tied high to V
requiring a simple 2-wire connection, as shown in
The ADXL345 conforms to the UM10204 I
and User Manual, Rev. 03—19 June 2007, available from NXP
Semiconductor. It supports standard (100 kHz) and fast (400 kHz)
data transfer modes if the bus parameters given in
and
supported, as shown in
high, the 7-bit I
the R/
read. An alternate I
can be chosen by grounding the ALT ADDRESS pin (Pin 12).
This translates to 0xA6 for a write and 0xA7 for a read.
There are no internal pull-up or pull-down resistors for any
unused pins; therefore, there is no known state or default state
for the CS or ALT ADDRESS pin if left floating or unconnected.
It is required that the CS pin be connected to V
the ALT ADDRESS pin be connected to either V
when using I
Table 11. I
Parameter
Digital Input
Low Level Input Voltage (V
High Level Input Voltage (V
Low Level Input Current (I
High Level Input Current (I
Digital Output
Low Level Output Voltage (V
Low Level Output Current (I
Pin Capacitance
1
2
Limits based on characterization results; not production tested.
C
Table 12
NOTES
1. THIS START IS EITHER A RESTART OR A STOP FOLLOWED BY A START.
2. THE SHADED AREAS REPRESENT WHEN THE DEVICE IS LISTENING.
SINGLE-BYTE WRITE
MASTER START
SLAVE
MULTIPLE-BYTE WRITE
MASTER START
SLAVE
SINGLE-BYTE READ
MASTER START
SLAVE
MULTIPLE-BYTE READ
MASTER START
SLAVE
W bit. This translates to 0x3A for a write and 0x3B for a
2
C Digital Input/Output
2
are met. Single- or multiple-byte reads/writes are
C.
2
C address for the device is 0x1D, followed by
SLAVE ADDRESS + WRITE
SLAVE ADDRESS + WRITE
SLAVE ADDRESS + WRITE
SLAVE ADDRESS + WRITE
2
C address of 0x53 (followed by the R/ W bit)
DD I/O
Figure 40
IL
IH
IL
)
IH
OL
)
)
, the ADXL345 is in I
)
OL
)
)
. With the ALT ADDRESS pin
ACK
ACK
ACK
ACK
REGISTER ADDRESS
REGISTER ADDRESS
REGISTER ADDRESS
REGISTER ADDRESS
2
C-Bus Specification
DD I/O
2
DD I/O
C mode,
Figure 39
Table 11
and that
Test Conditions
V
V
V
V
V
f
or GND
IN
ACK
ACK
ACK
ACK
IN
IN
DD I/O
DD I/O
OL
Figure 40. I
= 1 MHz, V
= V
= 0 V
= V
START
START
< 2 V, I
≥ 2 V, I
DD I/O
.
OL, max
Rev. B | Page 18 of 40
1
1
SLAVE ADDRESS + READ
SLAVE ADDRESS + READ
DATA
DATA
2
OL
OL
C Device Addressing
IN
= 3 mA
= 3 mA
= 2.5 V
Due to communication speed limitations, the maximum output
data rate when using 400 kHz I
with a change in the I
using I
Operation at an output data rate above the recommended maxi-
mum may result in undesirable effect on the acceleration data,
including missing samples or additional noise.
If other devices are connected to the same I
operating voltage level of these other devices cannot exceed V
by more than 0.3 V. External pull-up resistors, R
proper I
and User Manual, Rev. 03—19 June 2007, when selecting pull-up
resistor values to ensure proper operation.
ACK
ACK
STOP
ACK
ACK
2
C at 100 kHz would limit the maximum ODR to 200 Hz.
2
C operation. Refer to the UM10204 I
DATA
Figure 39. I
ALT ADDRESS
ADXL345
0.7 × V
Min
−0.1
3
DATA
DATA
SDA
SCL
2
C Connection Diagram (Address 0x53)
CS
ACK
2
C communication speed. For example,
DD I/O
STOP
NACK
ACK
R
V
P
DD I/O
2
Limit
C is 800 Hz and scales linearly
STOP
R
Max
0.3 × V
0.1
0.2 × V
400
8
P
1
DATA
PROCESSOR
D IN/OUT
D OUT
DD I/O
DD I/O
2
C bus, the nominal
2
C-Bus Specification
P
, are necessary for
NACK
STOP
Unit
V
V
μA
μA
V
mV
mA
pF
DD I/O