AD977AARZ Analog Devices Inc, AD977AARZ Datasheet - Page 13

• Manufacturer Part Number: AD977AARZ
• Description: 200 KSPS 16 BIT ADC
• Manufacturer: Analog Devices Inc

Specifications of AD977AARZ

• Number Of Bits: 16
• Sampling Rate (per Second): 200k
• Data Interface: Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 100mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-SOIC (0.300", 7.50mm Width)
• Number Of Elements: 1
• Resolution: 16Bit
• Architecture: SAR
• Sample Rate: 200KSPS
• Input Polarity: Unipolar/Bipolar
• Input Type: Voltage
• Differential Input: No
• Power Supply Requirement: Analog and Digital
• Single Supply Voltage (typ): 5V
• Single Supply Voltage (min): 4.75V
• Single Supply Voltage (max): 5.25V
• Dual Supply Voltage (typ): Not RequiredV
• Dual Supply Voltage (min): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Power Dissipation: 100mW
• Differential Linearity Error: ±3LSB
• Integral Nonlinearity Error: ±3LSB
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 20
• Package Type: SOIC W
• Input Signal Type: Single-Ended
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

EXTERNAL CONTINUOUS CLOCK DATA READ DURING
CONVERSION WITH SYNC OUTPUT GENERATED
Figure 9 illustrates the method by which data from conversion
“n-1” can be read during conversion “n” while using a continu-
ous external clock with the generation of a SYNC output. What
permits the generation of a SYNC output is a transition of
DATACLK while either CS is high or while both CS and R/C
are low.
With a continuous clock the CS pin cannot be tied low as it
could be with a discontinuous clock. Use of a continuous clock
while a conversion is occurring can increase the DNL and
Transition Noise of the AD977/AD977A.
In Figure 9 a conversion is initiated by taking R/C low with CS
held low. While this condition exists a transition of DATACLK,
clock pulse #0, will enable the generation of a SYNC pulse.
Less then 83 ns after R/C is taken low the BUSY output will go
low to indicate that the conversion process has began. Figure 9
shows R/C then going high and after a delay of greater than
DATACLK
BUSY
SYNC
DATA
TAG
EXT
R/C
CS
t
16
t
13
t
t
2
12
INT
t
14
t
1
0
t
15
t
17
1
t
t
23
12
TAG 0
t
t
18
2
24
BIT 15
(MSB)
TAG 1
15 ns (t
SYNC output. The SYNC output will appear approximately
50 ns after this rising edge and will be valid on the falling edge
of clock pulse #1 and the rising edge of clock pulse #2. The
MSB will be valid approximately 40 ns after the rising edge of
clock pulse #2 and can be latched off either the falling edge of
clock pulse #2 or the rising edge of clock pulse #3. The LSB
will be valid on the falling edge of clock pulse #17 and the rising
edge of clock pulse #18. Approximately 40 ns after the rising
edge of clock pulse #18, the DATA output pin will reflect the
state of the TAG input pin during the rising edge of clock
pulse #2.
For both the AD977 and the AD977A the data should be
clocked out during the 1st half of BUSY so as not to degrade
conversion performance. For the AD977 this requires use of a
4.8 MHz DATACLK or greater with data being read out as
soon as the conversion process begins. For the AD977A it
requires use of a 10 MHz DATACLK or greater.
3
t
20
15
), clock pulse #1 can be taken high to request the
(LSB)
TAG 16
BIT 0
t
18
18
TAG 0
TAG 17
AD977/AD977A
TAG 1
TAG 18
t
19
TAG 2
TAG 19