AD977AARZ Analog Devices Inc, AD977AARZ Datasheet - Page 11

• Manufacturer Part Number: AD977AARZ
• Description: 200 KSPS 16 BIT ADC
• Manufacturer: Analog Devices Inc

Specifications of AD977AARZ

• Number Of Bits: 16
• Sampling Rate (per Second): 200k
• Data Interface: Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 100mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-SOIC (0.300", 7.50mm Width)
• Number Of Elements: 1
• Resolution: 16Bit
• Architecture: SAR
• Sample Rate: 200KSPS
• Input Polarity: Unipolar/Bipolar
• Input Type: Voltage
• Differential Input: No
• Power Supply Requirement: Analog and Digital
• Single Supply Voltage (typ): 5V
• Single Supply Voltage (min): 4.75V
• Single Supply Voltage (max): 5.25V
• Dual Supply Voltage (typ): Not RequiredV
• Dual Supply Voltage (min): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Power Dissipation: 100mW
• Differential Linearity Error: ±3LSB
• Integral Nonlinearity Error: ±3LSB
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 20
• Package Type: SOIC W
• Input Signal Type: Single-Ended
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

EXTERNAL DISCONTINUOUS CLOCK DATA READ
DURING CONVERSION WITH SYNC OUTPUT
GENERATED
Figure 7 illustrates the method by which data from conversion
“n-1” can be read during conversion “n” while using a discon-
tinuous external clock, with the generation of a SYNC output.
What permits the generation of a SYNC output is a transition of
DATACLK while either CS is High or while both CS and R/C
are low. In Figure 7 a conversion is initiated by taking R/C low
with CS tied low. While this condition exists a transition of
DATACLK, clock pulse #0, will enable the generation of a
SYNC pulse. Less then 83 ns after R/C is taken low the BUSY
output will go low to indicate that the conversion process has
DATACLK
DATA
BUSY
SYNC
DATACLK
TAG
EXT
R/C
BUSY
SYNC
DATA
EXT
R/C
t
15
t
15
t
2
0
t
2
0
t
t
1
15
t
15
t
INT
17
t
1
13
t
t
15
12
t
t
t
14
12
17
t
13
1
t
12
t
18
t
t
t
TAG 0
2
23
12
14
t
t
BIT 15
(MSB)
18
24
2
BIT 15
(MSB)
TAG 1
CS
3
t
20
3
BIT 14
began. Figure 7 shows R/C then going high and after a delay of
greater than 15 ns (t
request the SYNC output. The SYNC output will appear
approximately 40 ns after this rising edge and will be valid on
the falling edge of clock pulse #1 and the rising edge of clock
pulse #2. The MSB will be valid approximately 40 ns after the
rising edge of clock pulse #2 and can be latched off either the
falling edge of clock pulse #2 or the rising edge of clock pulse
#3. The LSB will be valid on the falling edge of clock pulse #17
and the rising edge of clock pulse #18. Approximately 40 ns
after the rising edge of clock pulse #18, the DATA output
pin will reflect the state of the TAG input pin during the
rising edge of clock pulse #2.
BIT 14
TAG 2
4
(LSB)
BIT 0
15
17
t
18
18
) clock pulse #1 can be taken high to
TAG 16
TAG 0
(LSB)
BIT 0
18
t
INT
18
TAG 17
TAG 0
AD977/AD977A
t
22
TAG 18
TAG 1
TAG 19
TAG 2
CS