AD5620CRM-1 Analog Devices Inc, AD5620CRM-1 Datasheet - Page 9

• Manufacturer Part Number: AD5620CRM-1
• Description: IC,D/A CONVERTER,SINGLE,12-BIT,CMOS,TSSOP,8PIN
• Manufacturer: Analog Devices Inc
• Series: nanoDAC™r

Specifications of AD5620CRM-1

• Design Resources: Single-Ended-to-Differential Converters for Voltage Output and Current Output DACs Using AD8042 (CN0143) Amplitude Control Circuit for AD9834 Waveform Generator (CN0156)
• Settling Time: 8µs
• Number Of Bits: 12
• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Converters: 1
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 2.5mW
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 8-MSOP, Micro8™, 8-uMAX, 8-uSOP,
• Number Of Channels: 1
• Resolution: 12b
• Conversion Rate: 125KSPS
• Interface Type: Serial (3-Wire, SPI, QSPI, Microwire)
• Single Supply Voltage (typ): 3V
• Dual Supply Voltage (typ): Not RequiredV
• Architecture: Resistor-String
• Power Supply Requirement: Single
• Output Type: Voltage
• Integral Nonlinearity Error: ±1LSB
• Single Supply Voltage (min): 2.7V
• Single Supply Voltage (max): 3.3V
• Dual Supply Voltage (min): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 8
• Package Type: MSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Table 6. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
Mnemonic
V
V
V
V
SYNC
SCLK
DIN
GND
DD
REFOUT
FB
OUT
V
REFOUT
Figure 3. SOT-23 Pin Configuration
V
V
V
OUT
DD
FB
1
2
3
4
(Not to Scale)
AD5620/
AD5640/
AD5660
TOP VIEW
Description
Power Supply Input. These parts can operate from 2.7 V to 5.5 V. V
Reference Voltage Output.
Feedback Connection for the Output Amplifier. V
Analog Output Voltage from DAC. The output amplifier has rail-to-rail operation.
Level-Triggered Control Input (Active Low). This is the frame synchronization signal for the input data. When
SYNC goes low, it enables the input shift register and data is transferred in on the falling edges of the following
clocks. The DAC is updated following the 24
AD5620/AD5640 unless SYNC is taken high before this edge. In this case, the rising edge of SYNC acts as an
interrupt, and the write sequence is ignored by the DAC.
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data
can be transferred at rates up to 30 MHz.
Serial Data Input. The AD5660 has a 24-bit shift register, and the AD5620/AD5640 have a 16-bit shift register.
Data is clocked into the register on the falling edge of the serial clock input.
Ground Reference Point for all Circuitry on the Part.
8
7
6
5
GND
DIN
SCLK
SYNC
Rev. F | Page 9 of 28
th
clock cycle for the AD5660 and the 16
FB
should be connected to V
V
REFOUT
Figure 4. MSOP Pin Configuration
V
V
V
DD
OUT
DD
FB
should be decoupled to GND.
1
2
3
4
AD5620/AD5640/AD5660
(Not to Scale)
AD5620/
AD5640/
AD5660
TOP VIEW
OUT
for normal operation.
th
8
7
6
5
clock cycle for
GND
DIN
SCLK
SYNC