A6278ELPTR-T Allegro Microsystems Inc, A6278ELPTR-T Datasheet - Page 9

• Manufacturer Part Number: A6278ELPTR-T
• Description: IC,Laser Diode/LED Driver,BICMOS,TSSOP,16PIN,PLASTIC
• Manufacturer: Allegro Microsystems Inc
• Type: Linear (Non-Switching)r

Specifications of A6278ELPTR-T

• Constant Current: Yes
• Topology: 8-Bit Shift Register
• Number Of Outputs: 8
• Internal Driver: Yes
• Type - Primary: General Purpose
• Frequency: 25MHz
• Voltage - Supply: 3 V ~ 5.5 V
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP Exposed Pad, 16-eTSSOP, 16-HTSSOP
• Operating Temperature: -40°C ~ 85°C
• Current - Output / Channel: 75.5mA
• Internal Switch(s): Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Output: -
• Efficiency: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 620-1263-2; A6278ELPTR-T

A6278
A6279
Undervoltage Lockout
The A6278 and A6279 include an internal under-voltage lockout
(UVLO) circuit that disables the outputs in the event that the
logic supply voltage drops below a minimum acceptable level.
This feature prevents the display of erroneous information, a
necessary function for some critical applications.
Upon recovery of the logic supply voltage after a UVLO event,
and on power-up, all internal shift registers and latches are set
to 0. The A6278/A6279 is then in Normal mode.
Output Staggering Delay
The A6278/A6279 has a 20 ns delay between each output. The
staggering of the outputs reduces the in-rush of currents onto the
power and ground planes. This aids in power supply decoupling
and EMI/EMC reduction.
The output staggering delay occurs under the following condi-
tions:
• OUTPUT ENABLE is pulled low
• OUTPUT ENABLE is held low and LATCH ENABLE is
• OUTPUT ENABLE is held low, LATCH ENABLE is held high,
pulled high
and CLOCK is pulled high
and
Serial-Input, Constant-Current Latched
LED Drivers with Open LED Detection
The 20 ns delays are cumulative across all the outputs. Under any
of the above conditions, the state of OUT0 gets set after a typical
propagation delay, t
and so forth. In the A6279, OUT15 will get set after 300 ns (15 ×
20 ns) plus t
Note: The maximum CLOCK frequency is reduced in applica-
tions where both the OUTPUT ENABLE pin is held low and the
LATCH ENABLE pin is held high continuously, and the outputs
change state on the CLOCK edges. The staggering delay could
cause spurious output responses at CLOCK speeds greater than
1 MHz.
Thermal Shutdown
When the junction temperature of the A6278/A6279 reaches the
thermal shutdown temperature threshold, T
the outputs are shut off until the junction temperature cools down
below the recovery threshold, T
The shift register and output latches will remain active during
a TSD event. Therefore, there is no need to reset the data in the
output latches.
In LED OCD mode, if the junction temperature reaches the Ther-
mal Shut Down threshold, the outputs will turn off, as in Normal
mode operation. However, all of the shift registers will be set
with 0, the error bit value.
P(OE)
.
P(OE)
. OUT1 will get set 20 ns after OUT0,
115 Northeast Cutoff
1.508.853.5000; www.allegromicro.com
Allegro MicroSystems, Inc.
Worcester, Massachusetts 01615-0036 U.S.A.
JTSD
– T
JTSDhys
JTSD
(15°C typical).
(165°C typical),
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