A6278ELPTR-T Allegro Microsystems Inc, A6278ELPTR-T Datasheet - Page 7

• Manufacturer Part Number: A6278ELPTR-T
• Description: IC,Laser Diode/LED Driver,BICMOS,TSSOP,16PIN,PLASTIC
• Manufacturer: Allegro Microsystems Inc
• Type: Linear (Non-Switching)r

Specifications of A6278ELPTR-T

• Constant Current: Yes
• Topology: 8-Bit Shift Register
• Number Of Outputs: 8
• Internal Driver: Yes
• Type - Primary: General Purpose
• Frequency: 25MHz
• Voltage - Supply: 3 V ~ 5.5 V
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP Exposed Pad, 16-eTSSOP, 16-HTSSOP
• Operating Temperature: -40°C ~ 85°C
• Current - Output / Channel: 75.5mA
• Internal Switch(s): Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Output: -
• Efficiency: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 620-1263-2; A6278ELPTR-T

A6278
A6279
Normal Mode
Serial data present at the
to the shift register on the logic 0-to-logic 1 transition of the
CLOCK input pulse. On succeeding CLOCK pulses, the register
shifts data towards the SERIAL DATA OUT pin. The serial data
must appear at the input prior to the rising edge of the CLOCK
input waveform.
Data present in any register is transferred to the respective latch
when the LATCH ENABLE input is high (serial-to-parallel con-
version). The latches continue to accept new data as long as the
LATCH ENABLE input is held high.
Applications where the latches are bypassed (LATCH ENABLE
tied high) will require that the OUTPUT ENABLE input be high
during serial data entry. When the OUTPUT ENABLE input is
high, the output sink drivers are disabled (OFF).
The data stored in the latches is not affected by the OUTPUT
ENABLE input. With the OUTPUT ENABLE input active (low),
the outputs are controlled by the state of their respective latches.
LED Open Circuit Detection (Test) Mode
The LED Open Circuit Detection (OCD) mode, or Test mode,
is entered by clocking in the LED OCD mode initialization
sequence on the OUTPUT ENABLE (OE) and LATCH ENABLE
(LE) pins. In Normal mode, the OE and LE pins do not change
states while the CLOCK signal is cycling. The initialization
sequence is shown in panel A of the LED OCD timing require-
ments diagram on page 7.
Note: Each step event during mode sequencing happens on the
leading edge of the CLOCK signal. Five step events (CLOCK
pulses) are required to enter OCD mode and five step events are
required to return to Normal mode.
A pattern, such as all highs, should first be loaded into the reg-
isters and latched leaving LE low. The device is then sequenced
into LED OCD mode. It should be noted that data is still being
sent through the shift registers while entering the LED OCD
mode. However, this data is not latched when the LE pin goes
high and sees a CLOCK pulse during the initialization sequence.
and
SERIAL DATA IN
input is transferred
Functional Description
Serial-Input, Constant-Current Latched
LED Drivers with Open LED Detection
Open circuit detection does not take place until the sequence in
Panel B on page 7 is performed. During this sequence, the OE
pin must be held low for a minimum of 2 μs (t
proper settling of the output currents and be given a minimum of
three CLOCK pulses. During the period that the OE pin is low
(active), OCD testing begins. The V
output pins is compared to the Open LED Detection Theshold,
V
an error bit value of 0 is set in the corresponding shift register. A
value of 1 will be set if no error is detected. If a particular output
is not enabled, a 0 will be set. The error codes are summarized in
the following table:
After the testing process, setting the OE pin high causes the shift
registers to latch the error code data where it can then be clocked
out of the SERIAL DATA OUT pin. The OCD latching sequence
(OE low, 3 CLOCK pulses, OE high as shown in panel B of the
LED OCD timing diagram) can then be repeated if necessary to
look for intermittent contact problems.
The state of the outputs can be programmed with new data at any
time while in LED OCD mode (the same as in Normal mode).
This allows specific patterns to be tested for open circuits. The
pattern that is latched will then be tested during the OCD latching
sequence and the resulting bit values can be clocked out of the
SERIAL DATA OUT pin.
Note: LED Open Circuit Detection will not work properly if the
current is being externally limited by resistors to within the set
current limit for the device.
To return to Normal mode, perform the clocking sequence shown
in panel C of the timing diagram on the OE and LE pins.
CE(OCD)
Output State Test Condition Error Code Meaning
Output State
OFF
. If the V
ON
CE
Test Condition
V
V
of an enabled output is lower than V
CE
CE
< V
≥ V
N/A
115 Northeast Cutoff
1.508.853.5000; www.allegromicro.com
Allegro MicroSystems, Inc.
Worcester, Massachusetts 01615-0036 U.S.A.
CE(OCD)
CE(OCD)
CE
Error Code
voltage on each of the
0
0
1
W(OE1)
Open/TSD
Meaning
Normal
) to ensure
N/A
CE(OCD)
7
,