HMC5843 Honeywell Microelectronics & Precision Sensors, HMC5843 Datasheet - Page 19

• Manufacturer Part Number: HMC5843
• Description: Magnetic Sensor
• Manufacturer: Honeywell Microelectronics & Precision Sensors

Specifications of HMC5843

• Msl: MSL 3 - 168 Hours
• Sensitivity Range: +/- 10 %
• Sensor Terminals: PCB
• Magnetic Field Max: 4G
• Axis Configuration: Three
• Sensor Output: Digital

HMC5843
Data Output Register Operation
When one or more of the output registers are read, new data cannot be placed in any of the output data registers until all
six data output registers are read. This requirement also impacts DRDY and RDY, which cannot be cleared until new
data is placed in all the output registers.
Status Register
The status register is an 8 -bit read-only register. This register is used to indicate device status. SR0 through SR7
indicate bit locations, with S R denoting the bits that are in the status register. SR7 denotes the first bit of the data stream.
Identification Register A
The identification register A is used to identify the device. IRA0 through IRA7 indicate bit locations, with IRA denoting the
bits that are in the identification register A. IRA7 denotes the first bit of the data stream. The number in parenthesis
indicates the default value of that bit.
The identification value for this device is stored in this register. This is a read-only register.
Register values. ASCII value H
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SR7
(0)
Location
SR7 to
SR3
SR2
SR1
SR0
IRA7
0
IRA6
1
SR6
(0)
Name
0
REN
LOCK
RDY
Table 22: Identification Register A Default Values
Table 21: Status Register Bit Designations
IRA5
0
SR5
(0)
Description
These bits must be cleared for correct operation.
Regulator Enabled Bit. This bit is set when the internal
voltage regulator is enabled. This bit is cleared when the
internal regulator is disabled.
Data output register lock. This bit is set when this some but
not all for of the six data output registers have been read.
When this bit is set, the six data output registers are locked
and any new data will not be placed in these register until
on of four conditions are met: one, all six have been read
or the mode changed, two, a POR is issued, three, the
mode is changed, or four, the measurement is changed.
Ready Bit. Set when data is written to all six data registers.
Cleared when device initiates a write to the data output
registers, when in off mode, and after one or more of the
data output registers are written to. When RDY bit is clear
it shall remain cleared for a minimum of 5 µs. DRDY pin
can be used as an alternative to the status register for
monitoring the device for conversion data.
Table 20: Status Register
IRA4
0
SR4
(0)
SR3
(0)
IRA3
1
SR2
REN (0)
IRA2
0
SR1
LOCK (0)
IRA1
0
SR0
RDY(0)
IRA0
0
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