APDS-9303-020 Avago Technologies US Inc., APDS-9303-020 Datasheet
APDS-9303-020
Specifications of APDS-9303-020
Related parts for APDS-9303-020
APDS-9303-020 Summary of contents
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... APDS-9303 ambient light photo sensor module. You can contact them through your local sales representatives for additional details. Ordering Information Part Number Packaging Type APDS-9303-020 Tape and Reel Features • Approximate the human-eye response • Precise Illuminance measurement under diverse light- ing conditions • ...
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Functional Block Diagram Ch0 (Visible + IR Ch1 (IR) GND I/O Pins Configuration Table Pin Symbol Type 1 V Supply DD 2 GND Ground 3 ADDR SEL I 4 SCL I 5 SDA I/O 6 INT O Absolute ...
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Operating Characteristics, High Gain (16x 25°C, (unless otherwise noted) (see Notes Parameter Symbol Oscillator frequency fosc Dark ADC count value Full scale ADC count value (Note 6) ADC count value ADC count value ratio: ...
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NOTES: 2. Optical measurements are made using small–angle incident radiation from light–emitting diode optical sources. Visible 640 nm LEDs and infrared 940 nm LEDs are used for final product testing for compatibility with high–volume production. is supplied by an AlInGaP ...
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... C Slave Address Byte Figure 3. Example Timing Diagram for SMBus Receive Byte Format (HIGH) (SUSTA) t (SUDAT) S Stop SCL ACK t (LOWMEXT R ACK by APDS-9303 R ACK by APDS-9303 Frame 2 Data Byte From APDS-9303 t (SUSTO ACK by APDS-9303 Frame 2 Command Byte NACK by Master Stop by Master Stop by Master ...
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... Figure 5 SMBUS Protocol Each Send and Write protocol is, essentially, a series of bytes. A byte sent to the APDS-9303 with the most sig- nificant bit (MSB) equal to 1 will be interpreted as a COMMAND byte. The lower four bits of the COMMAND byte form the register select address (see Table 2), which is used to select the destination for the subsequent byte(s) received ...
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For a complete description of SMBus protocols, please review the SMBus Specification at http://www.smbus.org/specs Slave Address A Acknowledge (this bit position may be 0 for an ACK or 1 for a NACK) P Stop Condition Rd Read ...
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... Figure 13. SMBus Block Read Protocol Register Set The APDS-9303 is controlled and monitored by sixteen registers (three are reserved) and a command register accessed through the serial interface. These registers provide for a variety of control functions and can be read to determine results of the ADC conversions. The register set is summarized in Table 2. ...
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... Register Address. This field selects the specific control or status register for following write and read commands according to Table 2. Control Register (0h) The CONTROL register contains two bits and is primarily used to power the APDS-9303 device up and down as shown in Table 4. Table 4. Control Register 7 ...
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... Table 6, then this feature can be used. For example, the manual timing control can be used to synchronize the APDS-9303 device with an external light source (e.g. LED). A start command to begin integration can be initiated by writing this bit field. Correspondingly, the integration can be stopped by simply writing the same bit field ...
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Interrupt Threshold Register (2h - 5h) The interrupt threshold registers store the values to be used as the high and low trigger points for the comparison function for interrupt generation. If the value generated by channel 0 crosses below or ...
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... SMBAlert by performing a modified Receive Byte operation, in which the Alert Response Address (ARA) is placed in the slave address field, and the APDS-9303 that generated the interrupt responds by returning its own address in the seven most significant bits of the receive data byte. If more than one device connected on the bus has pulled the SMBAlert line low, the highest priority (lowest address) device will win communication rights via standard arbitration during the slave address transfer ...
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Table 9. Interrupt Control Select INTR FIELD VALUE READ VALUE 00 Level Interrupt output disabled 01 Level Interrupt output enabled Table 10. Interrupt Persistence Select PERSIST FIELD VALUE INTERRUPT PERSIST FUNCTION 0000 Every ADC cycle generates interrupt 0001 Any value ...
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ADC Channel Data Registers (Ch - Fh) The ADC channel data are expressed as 16–bit values spread across two registers. The ADC channel 0 data registers, DATA0LOW and DATA0HIGH provide the lower and upper bytes, respectively, of the ADC value ...
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... APDS-9303 Package outline 0.25±0.15 5 2.20±0.1 6 1.05 1 0.1 Pin 1 Marker 0.18 2.60±0.1 2x0.6±0.05 Notes: All dimensions are in millimeters. Dimension tolerance is ±0.2 mm unless otherwise stated PCB pad layout The suggested PCB layout is given below: Notes: All linear dimensions are in millimeters. ...
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... APDS-9303 Tape and Reel Dimensions 16 ...
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... Moisture Proof Packaging Chart All APDS-9303 options are shipped in moisture proof package. Once opened, moisture absorption begins. This part is compliant to JEDEC Level 3. MOISTURE-PROOF PACKAGE YES NO BAKING IS NECESSARY PERFORM RECOMMENDED BAKING CONDITIONS CHART Recommended Storage Conditions Storage Temperature 10°C to 30°C Relative Humidity ...
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Recommended Reflow Profile 255 230 217 200 180 150 120 HEAT UP Process Zone Heat Up Solder Paste Dry Solder Reflow Cool Down Time maintained above liquidus point, 217°C Peak Temperature Time within 5°C ...
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... There is a constraint on the minimum size of the window, which is placed in front of the photo light sensor, so that it will not affect the angular response of the APDS- 9303. This minimum dimension that is recommended will ensure at least a ±35° light reception cone. ...
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... Pin 1 Marker Notes: 1. All dimensions are in millimeters 2. All package dimension tolerance in ± 0.2mm unless otherwise specified Figure A3. APDS-9303 Light Sensitive Area A2: Optical Window Material The material of the window is recommended to be poly- carbonate. The surface finish of the plastic should be smooth, without any texture. ...
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... ADDR_SEL Pin 2: GND ** Note: ADDR_SEL Float : Slave address is 0111001 Figure B1. Application circuit for APDS-9303 The power supply lines must be decoupled with a 0.1 uF capacitor placed as close to the device package as possible, as shown in Figure B1. The bypass capacitor should have low effective series resistance (ESR) and low ...