ISL29028IROZ-T7 Intersil, ISL29028IROZ-T7 Datasheet - Page 4

• Manufacturer Part Number: ISL29028IROZ-T7
• Description: IC SENSOR LIGHT-PROXIMITY 8ODFN
• Manufacturer: Intersil

Specifications of ISL29028IROZ-T7

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Electrical Specifications
NOTES:
I2C Electrical Specifications
PARAMETER
PARAMETER
6. A 550nm green LED is used in production test. The 550nm LED irradiance is calibrated to produce the same DATA count against
7. 850nm infrared LED is used in production test for proximity/IR sensitivity testing.
8. Ability to guarantee I
PSRR
t
t
t
t
t
t
a fluorescent light source of the same lux level.
V
HD:DAT
HD:STA
SU:DAT
SU:STO
SU:STA
PULSE
V
t
V
I
F
t
I
V
V
V
f
HIGH
IRDR
V
SDA
V
V
V
t
t
LOW
INT
REF
I
SCL
I
t
I
hys
AA
C
t
IH
I
SP
2
IL
OL
2
IH
R
2
IL
F
IRDR
i
i
C
C
C
Acceptable Voltage Range on IRDR Pin
Net I
Voltage of R
I
Supply Voltage Range for I
SCL and SDA Input Low Voltage
SCL and SDA Input High Voltage
SDA Current Sinking Capability
INT Current Sinking Capability
(ΔI
2
Supply Voltage Range for I
SCL Clock Frequency
SCL and SDA Input Low Voltage
SCL and SDA Input High Voltage
Hysteresis of Schmitt Trigger Input
Low-level output voltage (open-drain) at
4mA sink current
Input Leakage for each SDA, SCL pin
Pulse width of spikes that must be
suppressed by the input filter
SCL Falling Edge to SDA Output Data Valid
Capacitance for each SDA and SCL pin
Hold Time (Repeated) START Condition
LOW Period of the SCL clock
HIGH period of the SCL Clock
Set-up Time for a Repeated START
Condition
Data Hold Time
Data Set-up Time
Rise Time of both SDA and SCL Signals
Fall Time of both SDA and SCL Signals
Set-up Time for STOP Condition
C Clock Rate Range
IRDR
IRDR
)/(ΔV
On Time Per PROX Reading
IRDR
EXT
IRDR
DESCRIPTION
DESCRIPTION
4
leakage of ~1nA is limited by test hardware.
Pin
)
V
DD
For SCL and SDA unless otherwise noted, V
tolerance (Note 9).
= 3.0V, T
2
2
C Interface
C Interface
A
= +25°C, R
ISL29028
After this period, the first clock pulse
is generated
Measured at the 30% of VDD
crossing
(Note 10)
(Note 10)
Register bit PROX_DR = 0
V
V
PROX_DR = 0; V
OL
OL
EXT
= 0.4V
= 0.4V
= 499kΩ 1% tolerance. (Continued)
CONDITION
CONDITION
IRDR
= 0.5V to 4.3V
DD
= 3V, T
A
= +25°C, R
20 + 0.1xC
20 + 0.1xC
0.05V
1300
MIN
1.25
600
600
600
100
600
1.7
-10
30
MIN TYP MAX UNIT
1.25
DD
0.5
1.7
3
3
EXT
b
b
0.51
TYP MAX UNIT
100
5
5
4
= 499kΩ 1%
3.63
0.55
3.63
0.55
400
900
0.4
400
4.3
10
50
10
March 2, 2010
FN6780.1
mA/V
kHz
µA
pF
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
mA
mA
V
V
V
V
V
µs
V
V
V
V
V