AS5030-ATST austriamicrosystems, AS5030-ATST Datasheet - Page 15

• Manufacturer Part Number: AS5030-ATST
• Description: IC ENCODER ROTARY 8-BIT 16-TSSOP
• Manufacturer: austriamicrosystems
• Type: Linear, Rotary Encoder - Programmabler

Specifications of AS5030-ATST

• Sensing Range: 23.6mT ~ 44.5mT
• Voltage - Supply: 4.5 V ~ 5.5 V
• Current - Supply: 14mA
• Current - Output (max): 4mA
• Output Type: Digital, PWM
• Features: Programmable
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 16-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: AS5030-ATSTTR

AS5030
Datasheet - D e t a i l e d D e s c r i p t i o n
7.5 Serial 2-Wire Continuous Readout
The termination of each readout sequence by a timeout of CLK after the 22
is the safest method to ensure synchronization, as each timeout of CLK resets the serial interface.
However, it is not mandatory to apply a timeout of CLK and consequently synchronization after each reading. It is also possible to read several
consecutive angle values without synchronization by simply continuing the CLK pulses without timeout after the 22
equal to the 1
This is the fastest way to read multiple angle values, as there is no timeout period between the readings. It is still possible to synchronize the
serial data transmission by a timeout of CLK after a given number of readouts (e.g. synchronize after every 5
Figure 10. Timing Diagram in 2-wire SSI Continuous Readout
7.6 Serial 2-Wire Differential SSI Connection
With the addition of a RS-422 / RS-485 transceiver, a fully differential data transmission, according to the 21-bit SSI interface standard is
possible. To be compatible with this standard, the CLK signal must be inverted. This is done by reversing the Data+ and Data- lines of the
transceivers.
Note: This type of transmission is read-only.
Figure 11. 2-wire SSI Read-only Mode
www.austriamicrosystems.com/AS5030
VSS
+ 5 V
VDD
DIO write
DIO read
Micro
Controller
st
CLK
clock of the next measurement, etc.
DX
CS
VDD
VSS
t 0
Output
1
Input
t1
CMD4
DI
2
CLK
command phase
CMD 3
3
CMD2
4
D+
D-
D+
D-
MAX 3081 or similar
1st reading
CMD 1
5
t6
CMD 0
6
Revision 2.1
t5
D 15
nd
data phase
7
D+
D-
D+
D-
clock pulse as described in
D 14
8
D 0
22
11
12
10
9
CLK
DX
CS
D I O
23
Serial 2-Wire Connection (R/W Mode)
14
CMD 4
C1
th
2nd reading
24
command phase
reading, etc.)
15
C2
AS5030
nd
CMD 3
clock. The 23
25
VSS
13
VDD
3
CMD2
rd
100n
clock is
15 - 44